Search

Raj R. Gupta

Examiner (ID: 12575)

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4147843 [patent_doc_number] => 06128725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Microprocessor with an instruction for setting or clearing a bit field' [patent_app_type] => 1 [patent_app_number] => 9/012327 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4434 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128725.pdf [firstpage_image] =>[orig_patent_app_number] => 012327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012327
Microprocessor with an instruction for setting or clearing a bit field Jan 22, 1998 Issued
Array ( [id] => 1549644 [patent_doc_number] => 06374346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Processor with conditional execution of every instruction' [patent_app_type] => B1 [patent_app_number] => 09/012326 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6342 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374346.pdf [firstpage_image] =>[orig_patent_app_number] => 09012326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012326
Processor with conditional execution of every instruction Jan 22, 1998 Issued
Array ( [id] => 4122151 [patent_doc_number] => 06052771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Microprocessor with pipeline synchronization' [patent_app_type] => 1 [patent_app_number] => 9/008792 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8673 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052771.pdf [firstpage_image] =>[orig_patent_app_number] => 008792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008792
Microprocessor with pipeline synchronization Jan 19, 1998 Issued
Array ( [id] => 4211753 [patent_doc_number] => 06044460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'System and method for PC-relative address generation in a microprocessor with a pipeline architecture' [patent_app_type] => 1 [patent_app_number] => 9/007912 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3763 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044460.pdf [firstpage_image] =>[orig_patent_app_number] => 007912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007912
System and method for PC-relative address generation in a microprocessor with a pipeline architecture Jan 15, 1998 Issued
Array ( [id] => 4402491 [patent_doc_number] => 06279102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus employing a single table for renaming more than one class of register' [patent_app_type] => 1 [patent_app_number] => 9/002142 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3146 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279102.pdf [firstpage_image] =>[orig_patent_app_number] => 002142 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002142
Method and apparatus employing a single table for renaming more than one class of register Dec 30, 1997 Issued
Array ( [id] => 4371320 [patent_doc_number] => 06216219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability' [patent_app_type] => 1 [patent_app_number] => 9/000937 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 34132 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216219.pdf [firstpage_image] =>[orig_patent_app_number] => 000937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000937
Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability Dec 29, 1997 Issued
Array ( [id] => 3973639 [patent_doc_number] => 05978904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 8/996787 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 14975 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978904.pdf [firstpage_image] =>[orig_patent_app_number] => 996787 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996787
Data processor Dec 22, 1997 Issued
Array ( [id] => 4100485 [patent_doc_number] => 06018759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Thread switch tuning tool for optimal performance in a computer processor' [patent_app_type] => 1 [patent_app_number] => 8/996309 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13806 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018759.pdf [firstpage_image] =>[orig_patent_app_number] => 996309 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996309
Thread switch tuning tool for optimal performance in a computer processor Dec 21, 1997 Issued
Array ( [id] => 4147884 [patent_doc_number] => 06128728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Virtual shadow registers and virtual register windows' [patent_app_type] => 1 [patent_app_number] => 8/989732 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14335 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128728.pdf [firstpage_image] =>[orig_patent_app_number] => 989732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989732
Virtual shadow registers and virtual register windows Dec 11, 1997 Issued
Array ( [id] => 3923483 [patent_doc_number] => 05928358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Information processing apparatus which accurately predicts whether a branch is taken for a conditional branch instruction, using small-scale hardware' [patent_app_type] => 1 [patent_app_number] => 8/987260 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9786 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928358.pdf [firstpage_image] =>[orig_patent_app_number] => 987260 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987260
Information processing apparatus which accurately predicts whether a branch is taken for a conditional branch instruction, using small-scale hardware Dec 8, 1997 Issued
Array ( [id] => 4101193 [patent_doc_number] => 06163840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline' [patent_app_type] => 1 [patent_app_number] => 8/980168 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 15335 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163840.pdf [firstpage_image] =>[orig_patent_app_number] => 980168 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980168
Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline Nov 25, 1997 Issued
Array ( [id] => 4152064 [patent_doc_number] => 06035395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Computer system capable of using removable disk drive as boot device and method of controlling bootstrap' [patent_app_type] => 1 [patent_app_number] => 8/978743 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4011 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035395.pdf [firstpage_image] =>[orig_patent_app_number] => 978743 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978743
Computer system capable of using removable disk drive as boot device and method of controlling bootstrap Nov 25, 1997 Issued
Array ( [id] => 3997651 [patent_doc_number] => 05862334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Mediated access to an intelligent network' [patent_app_type] => 1 [patent_app_number] => 8/979153 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862334.pdf [firstpage_image] =>[orig_patent_app_number] => 979153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979153
Mediated access to an intelligent network Nov 25, 1997 Issued
Array ( [id] => 3924011 [patent_doc_number] => 05938761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method and apparatus for branch target prediction' [patent_app_type] => 1 [patent_app_number] => 8/976826 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5477 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938761.pdf [firstpage_image] =>[orig_patent_app_number] => 976826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976826
Method and apparatus for branch target prediction Nov 23, 1997 Issued
Array ( [id] => 4237548 [patent_doc_number] => 06112298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method for managing an instruction execution pipeline during debugging of a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/974742 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 70 [patent_no_of_words] => 41318 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112298.pdf [firstpage_image] =>[orig_patent_app_number] => 974742 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974742
Method for managing an instruction execution pipeline during debugging of a data processing system Nov 18, 1997 Issued
Array ( [id] => 4068798 [patent_doc_number] => 05970241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Maintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/974589 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 69 [patent_no_of_words] => 41365 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970241.pdf [firstpage_image] =>[orig_patent_app_number] => 974589 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974589
Maintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing system Nov 18, 1997 Issued
Array ( [id] => 4281114 [patent_doc_number] => 06260135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Parallel processing unit and instruction issuing system' [patent_app_type] => 1 [patent_app_number] => 8/970802 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6723 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260135.pdf [firstpage_image] =>[orig_patent_app_number] => 970802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970802
Parallel processing unit and instruction issuing system Nov 13, 1997 Issued
Array ( [id] => 3943742 [patent_doc_number] => 05878255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Update unit for providing a delayed update to a branch prediction array' [patent_app_type] => 1 [patent_app_number] => 8/969039 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 66 [patent_no_of_words] => 101131 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878255.pdf [firstpage_image] =>[orig_patent_app_number] => 969039 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969039
Update unit for providing a delayed update to a branch prediction array Nov 11, 1997 Issued
Array ( [id] => 4042324 [patent_doc_number] => 05931926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO' [patent_app_type] => 1 [patent_app_number] => 8/966548 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10678 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931926.pdf [firstpage_image] =>[orig_patent_app_number] => 966548 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966548
Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO Nov 9, 1997 Issued
Array ( [id] => 1592382 [patent_doc_number] => 06360311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Processor architecture with independently addressable memory banks for storing instructions to be executed' [patent_app_type] => B1 [patent_app_number] => 08/963937 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5842 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360311.pdf [firstpage_image] =>[orig_patent_app_number] => 08963937 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963937
Processor architecture with independently addressable memory banks for storing instructions to be executed Nov 3, 1997 Issued
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