Raj R. Gupta

Array ( [id] => 3962525 [patent_doc_number] => 05983015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Latch-free sequence generation for high concurrency systems' [patent_app_type] => 1 [patent_app_number] => 8/962534 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7902 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983015.pdf [firstpage_image] =>[orig_patent_app_number] => 962534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3962085 [patent_doc_number] => 05974542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication' [patent_app_type] => 1 [patent_app_number] => 8/960818 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13392 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974542.pdf [firstpage_image] =>[orig_patent_app_number] => 960818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4402248 [patent_doc_number] => 06279084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Shadow commands to optimize sequencing of requests in a switch-based multi-processor system' [patent_app_type] => 1 [patent_app_number] => 8/957062 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 55 [patent_no_of_words] => 33079 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279084.pdf [firstpage_image] =>[orig_patent_app_number] => 957062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042618 [patent_doc_number] => 05931943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Floating point NaN comparison' [patent_app_type] => 1 [patent_app_number] => 8/955287 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11956 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931943.pdf [firstpage_image] =>[orig_patent_app_number] => 955287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1326758 [patent_doc_number] => RE038171 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Introduction sequencer for network structure microprocessor' [patent_app_type] => E1 [patent_app_number] => 08/954438 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4591 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 851 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038171.pdf [firstpage_image] =>[orig_patent_app_number] => 08954438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3887780 [patent_doc_number] => 05838945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Tunable software control of harvard architecture cache memories using prefetch instructions' [patent_app_type] => 1 [patent_app_number] => 8/953220 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2776 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838945.pdf [firstpage_image] =>[orig_patent_app_number] => 953220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3801893 [patent_doc_number] => 05841670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Emulation devices, systems and methods with distributed control of clock domains' [patent_app_type] => 1 [patent_app_number] => 8/950469 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 94 [patent_no_of_words] => 38624 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841670.pdf [firstpage_image] =>[orig_patent_app_number] => 950469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1066747 [patent_doc_number] => 06851042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Audio, fax and modem capabilities with a digital signal processor of a sound card of a computer system' [patent_app_type] => utility [patent_app_number] => 08/949534 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4926 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851042.pdf [firstpage_image] =>[orig_patent_app_number] => 08949534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4226000 [patent_doc_number] => 06029244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Microprocessor including an efficient implementation of extreme value instructions' [patent_app_type] => 1 [patent_app_number] => 8/948679 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 9270 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029244.pdf [firstpage_image] =>[orig_patent_app_number] => 948679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4085516 [patent_doc_number] => 06009517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Mixed execution stack and exception handling' [patent_app_type] => 1 [patent_app_number] => 8/944335 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7182 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009517.pdf [firstpage_image] =>[orig_patent_app_number] => 944335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3989509 [patent_doc_number] => 05905880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Robust multiple word instruction and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/937682 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1453 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905880.pdf [firstpage_image] =>[orig_patent_app_number] => 937682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423468 [patent_doc_number] => 06311261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Apparatus and method for improving superscalar processors' [patent_app_type] => 1 [patent_app_number] => 8/932068 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 36416 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311261.pdf [firstpage_image] =>[orig_patent_app_number] => 932068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156217 [patent_doc_number] => 06122729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Prefetch buffer which stores a pointer indicating an initial predecode position' [patent_app_type] => 1 [patent_app_number] => 8/929413 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122729.pdf [firstpage_image] =>[orig_patent_app_number] => 929413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 953346 [patent_doc_number] => 06961846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-01 [patent_title] => 'Data processing unit, microprocessor, and method for performing an instruction' [patent_app_type] => utility [patent_app_number] => 08/928427 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2355 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961846.pdf [firstpage_image] =>[orig_patent_app_number] => 08928427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4388536 [patent_doc_number] => 06275925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Program execution method and program execution device' [patent_app_type] => 1 [patent_app_number] => 8/926927 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3474 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275925.pdf [firstpage_image] =>[orig_patent_app_number] => 926927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998160 [patent_doc_number] => 05949996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Processor having a variable number of stages in a pipeline' [patent_app_type] => 1 [patent_app_number] => 8/927065 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 42 [patent_no_of_words] => 20547 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949996.pdf [firstpage_image] =>[orig_patent_app_number] => 927065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015173 [patent_doc_number] => 05925122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Data processing unit which pre-fetches instructions of different lengths to conduct processing' [patent_app_type] => 1 [patent_app_number] => 8/919776 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6755 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925122.pdf [firstpage_image] =>[orig_patent_app_number] => 919776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4391889 [patent_doc_number] => 06289437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Data processing system and method for implementing an efficient out-of-order issue mechanism' [patent_app_type] => 1 [patent_app_number] => 8/968736 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 64 [patent_no_of_words] => 19495 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289437.pdf [firstpage_image] =>[orig_patent_app_number] => 968736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057340 [patent_doc_number] => 05875315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Parallel and scalable instruction scanning unit' [patent_app_type] => 1 [patent_app_number] => 8/915092 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 70 [patent_no_of_words] => 102930 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875315.pdf [firstpage_image] =>[orig_patent_app_number] => 915092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3923411 [patent_doc_number] => 05928353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Clear processing of a translation lookaside buffer with less waiting time' [patent_app_type] => 1 [patent_app_number] => 8/999621 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928353.pdf [firstpage_image] =>[orig_patent_app_number] => 999621 [rel_patent_id] =>[rel_patent_doc_number] =>)