| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3919337
[patent_doc_number] => 05898893
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Fifo memory system and method for controlling'
[patent_app_type] => 1
[patent_app_number] => 8/899362
[patent_app_country] => US
[patent_app_date] => 1997-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7326
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/898/05898893.pdf
[firstpage_image] =>[orig_patent_app_number] => 899362
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/899362 | Fifo memory system and method for controlling | Jul 22, 1997 | Issued |
Array
(
[id] => 3997226
[patent_doc_number] => 05961631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Data processing apparatus and method for pre-fetching an instruction in to an instruction cache'
[patent_app_type] => 1
[patent_app_number] => 8/893982
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6466
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/961/05961631.pdf
[firstpage_image] =>[orig_patent_app_number] => 893982
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893982 | Data processing apparatus and method for pre-fetching an instruction in to an instruction cache | Jul 15, 1997 | Issued |
| 08/887680 | EXTENDING COMPUTER ARCHITECTURE FROM 32-BITS TO 64-BITS BY USING THE MOST SIGNIFICANT BIT OF THE STACK POINTER REGISTER TO INDICATE WORD SIZE | Jul 2, 1997 | Abandoned |
Array
(
[id] => 4026687
[patent_doc_number] => 05890187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Storage device utilizing a motion control circuit having an integrated digital signal processing and central processing unit'
[patent_app_type] => 1
[patent_app_number] => 8/882901
[patent_app_country] => US
[patent_app_date] => 1997-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 25
[patent_no_of_words] => 11534
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/890/05890187.pdf
[firstpage_image] =>[orig_patent_app_number] => 882901
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882901 | Storage device utilizing a motion control circuit having an integrated digital signal processing and central processing unit | Jun 25, 1997 | Issued |
Array
(
[id] => 4122218
[patent_doc_number] => 06052775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Method for non-intrusive cache fills and handling of load misses'
[patent_app_type] => 1
[patent_app_number] => 8/881723
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9133
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/052/06052775.pdf
[firstpage_image] =>[orig_patent_app_number] => 881723
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881723 | Method for non-intrusive cache fills and handling of load misses | Jun 24, 1997 | Issued |
Array
(
[id] => 4423787
[patent_doc_number] => 06240502
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Apparatus for dynamically reconfiguring a processor'
[patent_app_type] => 1
[patent_app_number] => 8/881145
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 8124
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/240/06240502.pdf
[firstpage_image] =>[orig_patent_app_number] => 881145
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881145 | Apparatus for dynamically reconfiguring a processor | Jun 24, 1997 | Issued |
Array
(
[id] => 3974377
[patent_doc_number] => 05901306
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Method and apparatus for reducing a computational result to the range boundaries of a signed 8-bit integer in case of overflow'
[patent_app_type] => 1
[patent_app_number] => 8/881721
[patent_app_country] => US
[patent_app_date] => 1997-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3203
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/901/05901306.pdf
[firstpage_image] =>[orig_patent_app_number] => 881721
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881721 | Method and apparatus for reducing a computational result to the range boundaries of a signed 8-bit integer in case of overflow | Jun 22, 1997 | Issued |
Array
(
[id] => 4215720
[patent_doc_number] => 06014738
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'Method for computing a difference in a digital processing system'
[patent_app_type] => 1
[patent_app_number] => 8/880627
[patent_app_country] => US
[patent_app_date] => 1997-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2783
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/014/06014738.pdf
[firstpage_image] =>[orig_patent_app_number] => 880627
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880627 | Method for computing a difference in a digital processing system | Jun 22, 1997 | Issued |
Array
(
[id] => 3898336
[patent_doc_number] => 05894568
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-13
[patent_title] => 'Apparatus and method for computing a difference in a digital processing system'
[patent_app_type] => 1
[patent_app_number] => 8/879420
[patent_app_country] => US
[patent_app_date] => 1997-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2786
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/894/05894568.pdf
[firstpage_image] =>[orig_patent_app_number] => 879420
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/879420 | Apparatus and method for computing a difference in a digital processing system | Jun 19, 1997 | Issued |
Array
(
[id] => 4240322
[patent_doc_number] => 06012141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Apparatus for detecting and executing traps in a superscalar processor'
[patent_app_type] => 1
[patent_app_number] => 8/878524
[patent_app_country] => US
[patent_app_date] => 1997-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5446
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/012/06012141.pdf
[firstpage_image] =>[orig_patent_app_number] => 878524
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/878524 | Apparatus for detecting and executing traps in a superscalar processor | Jun 18, 1997 | Issued |
Array
(
[id] => 3922897
[patent_doc_number] => 05928321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Task and stack manager for digital video decoding'
[patent_app_type] => 1
[patent_app_number] => 8/866419
[patent_app_country] => US
[patent_app_date] => 1997-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 8344
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/928/05928321.pdf
[firstpage_image] =>[orig_patent_app_number] => 866419
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/866419 | Task and stack manager for digital video decoding | May 29, 1997 | Issued |
Array
(
[id] => 4065103
[patent_doc_number] => 05870596
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Data processor allowing multifunctional instruction execution'
[patent_app_type] => 1
[patent_app_number] => 8/862680
[patent_app_country] => US
[patent_app_date] => 1997-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 43
[patent_no_of_words] => 17662
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 350
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/870/05870596.pdf
[firstpage_image] =>[orig_patent_app_number] => 862680
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/862680 | Data processor allowing multifunctional instruction execution | May 22, 1997 | Issued |
Array
(
[id] => 3796978
[patent_doc_number] => 05819081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Method of executing a branch instruction of jumping to a subroutine in a pipeline control system'
[patent_app_type] => 1
[patent_app_number] => 8/862842
[patent_app_country] => US
[patent_app_date] => 1997-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1374
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/819/05819081.pdf
[firstpage_image] =>[orig_patent_app_number] => 862842
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/862842 | Method of executing a branch instruction of jumping to a subroutine in a pipeline control system | May 22, 1997 | Issued |
Array
(
[id] => 3811687
[patent_doc_number] => 05781746
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Microprocessor with multiple bus configurations'
[patent_app_type] => 1
[patent_app_number] => 8/854371
[patent_app_country] => US
[patent_app_date] => 1997-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 5831
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 341
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/781/05781746.pdf
[firstpage_image] =>[orig_patent_app_number] => 854371
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854371 | Microprocessor with multiple bus configurations | May 11, 1997 | Issued |
Array
(
[id] => 3968534
[patent_doc_number] => 05978571
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Method and apparatus for synchronous circuit simulation design by eliminating unneeded timing behaviors prior to simulation run-time'
[patent_app_type] => 1
[patent_app_number] => 8/854419
[patent_app_country] => US
[patent_app_date] => 1997-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 9638
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/978/05978571.pdf
[firstpage_image] =>[orig_patent_app_number] => 854419
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854419 | Method and apparatus for synchronous circuit simulation design by eliminating unneeded timing behaviors prior to simulation run-time | May 11, 1997 | Issued |
Array
(
[id] => 3961966
[patent_doc_number] => 05974535
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Method and system in data processing system of permitting concurrent processing of instructions of a particular type'
[patent_app_type] => 1
[patent_app_number] => 8/853009
[patent_app_country] => US
[patent_app_date] => 1997-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9205
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/974/05974535.pdf
[firstpage_image] =>[orig_patent_app_number] => 853009
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/853009 | Method and system in data processing system of permitting concurrent processing of instructions of a particular type | May 8, 1997 | Issued |
Array
(
[id] => 4121499
[patent_doc_number] => 06023756
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Instruction processing method and system for variable-length instructions'
[patent_app_type] => 1
[patent_app_number] => 8/846419
[patent_app_country] => US
[patent_app_date] => 1997-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6161
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/023/06023756.pdf
[firstpage_image] =>[orig_patent_app_number] => 846419
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/846419 | Instruction processing method and system for variable-length instructions | Apr 29, 1997 | Issued |
Array
(
[id] => 4008346
[patent_doc_number] => 05892941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Multiple user software debugging system'
[patent_app_type] => 1
[patent_app_number] => 8/841615
[patent_app_country] => US
[patent_app_date] => 1997-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5288
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892941.pdf
[firstpage_image] =>[orig_patent_app_number] => 841615
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/841615 | Multiple user software debugging system | Apr 28, 1997 | Issued |
Array
(
[id] => 4325820
[patent_doc_number] => 06253314
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Instruction set and executing method of the same by microcomputer'
[patent_app_type] => 1
[patent_app_number] => 8/844103
[patent_app_country] => US
[patent_app_date] => 1997-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5403
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/253/06253314.pdf
[firstpage_image] =>[orig_patent_app_number] => 844103
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/844103 | Instruction set and executing method of the same by microcomputer | Apr 27, 1997 | Issued |
Array
(
[id] => 4057516
[patent_doc_number] => 05875326
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'Data processing system and method for completing out-of-order instructions'
[patent_app_type] => 1
[patent_app_number] => 8/840919
[patent_app_country] => US
[patent_app_date] => 1997-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8123
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/875/05875326.pdf
[firstpage_image] =>[orig_patent_app_number] => 840919
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840919 | Data processing system and method for completing out-of-order instructions | Apr 24, 1997 | Issued |