| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3788446
[patent_doc_number] => 05774712
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Instruction dispatch unit and method for mapping a sending order of operations to a receiving order'
[patent_app_type] => 1
[patent_app_number] => 8/770219
[patent_app_country] => US
[patent_app_date] => 1996-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5620
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774712.pdf
[firstpage_image] =>[orig_patent_app_number] => 770219
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/770219 | Instruction dispatch unit and method for mapping a sending order of operations to a receiving order | Dec 18, 1996 | Issued |
Array
(
[id] => 1043188
[patent_doc_number] => 06871275
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Microprocessor having a branch predictor using speculative branch registers'
[patent_app_type] => utility
[patent_app_number] => 08/764512
[patent_app_country] => US
[patent_app_date] => 1996-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4140
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/871/06871275.pdf
[firstpage_image] =>[orig_patent_app_number] => 08764512
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764512 | Microprocessor having a branch predictor using speculative branch registers | Dec 11, 1996 | Issued |
Array
(
[id] => 3970786
[patent_doc_number] => 05991871
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Application binary interface and method of interfacing binary application program to digital computer'
[patent_app_type] => 1
[patent_app_number] => 8/744445
[patent_app_country] => US
[patent_app_date] => 1996-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 25
[patent_no_of_words] => 12459
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/991/05991871.pdf
[firstpage_image] =>[orig_patent_app_number] => 744445
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744445 | Application binary interface and method of interfacing binary application program to digital computer | Nov 7, 1996 | Issued |
Array
(
[id] => 3830071
[patent_doc_number] => 05812812
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue'
[patent_app_type] => 1
[patent_app_number] => 8/740911
[patent_app_country] => US
[patent_app_date] => 1996-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3187
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812812.pdf
[firstpage_image] =>[orig_patent_app_number] => 740911
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/740911 | Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue | Nov 3, 1996 | Issued |
| 08/742715 | PROTOCAL ANALYZER FOR MONITORING DIGITAL TRANSMISSION NETWORKS | Oct 31, 1996 | Abandoned |
Array
(
[id] => 4254486
[patent_doc_number] => 06119168
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Communications system usable as system for simulating a plurality of other communications systems and communication processing system having such communications system'
[patent_app_type] => 1
[patent_app_number] => 8/742270
[patent_app_country] => US
[patent_app_date] => 1996-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 7132
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 274
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119168.pdf
[firstpage_image] =>[orig_patent_app_number] => 742270
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742270 | Communications system usable as system for simulating a plurality of other communications systems and communication processing system having such communications system | Oct 30, 1996 | Issued |
Array
(
[id] => 3805911
[patent_doc_number] => 05822773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Method and system for accelerating the copying of repetitively copied computer data'
[patent_app_type] => 1
[patent_app_number] => 8/734411
[patent_app_country] => US
[patent_app_date] => 1996-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 17263
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822773.pdf
[firstpage_image] =>[orig_patent_app_number] => 734411
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/734411 | Method and system for accelerating the copying of repetitively copied computer data | Oct 16, 1996 | Issued |
Array
(
[id] => 3878042
[patent_doc_number] => 05796979
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Data processing system having demand based write through cache with enforced ordering'
[patent_app_type] => 1
[patent_app_number] => 8/730994
[patent_app_country] => US
[patent_app_date] => 1996-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2202
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/796/05796979.pdf
[firstpage_image] =>[orig_patent_app_number] => 730994
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730994 | Data processing system having demand based write through cache with enforced ordering | Oct 15, 1996 | Issued |
Array
(
[id] => 4065324
[patent_doc_number] => 05870612
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Method and apparatus for condensed history buffer'
[patent_app_type] => 1
[patent_app_number] => 8/729309
[patent_app_country] => US
[patent_app_date] => 1996-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 10722
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/870/05870612.pdf
[firstpage_image] =>[orig_patent_app_number] => 729309
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/729309 | Method and apparatus for condensed history buffer | Oct 14, 1996 | Issued |
Array
(
[id] => 4018289
[patent_doc_number] => 05860014
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Method and apparatus for improved recovery of processor state using history buffer'
[patent_app_type] => 1
[patent_app_number] => 8/729307
[patent_app_country] => US
[patent_app_date] => 1996-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 10996
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/860/05860014.pdf
[firstpage_image] =>[orig_patent_app_number] => 729307
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/729307 | Method and apparatus for improved recovery of processor state using history buffer | Oct 14, 1996 | Issued |
Array
(
[id] => 3898261
[patent_doc_number] => 05805906
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions'
[patent_app_type] => 1
[patent_app_number] => 8/729308
[patent_app_country] => US
[patent_app_date] => 1996-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 24
[patent_no_of_words] => 13703
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805906.pdf
[firstpage_image] =>[orig_patent_app_number] => 729308
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/729308 | Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions | Oct 14, 1996 | Issued |
Array
(
[id] => 4037794
[patent_doc_number] => 05926634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Limited run branch prediction'
[patent_app_type] => 1
[patent_app_number] => 8/731367
[patent_app_country] => US
[patent_app_date] => 1996-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 7040
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926634.pdf
[firstpage_image] =>[orig_patent_app_number] => 731367
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/731367 | Limited run branch prediction | Oct 10, 1996 | Issued |
Array
(
[id] => 3758451
[patent_doc_number] => 05754811
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Instruction dispatch queue for improved instruction cache to queue timing'
[patent_app_type] => 1
[patent_app_number] => 8/730606
[patent_app_country] => US
[patent_app_date] => 1996-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4006
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754811.pdf
[firstpage_image] =>[orig_patent_app_number] => 730606
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730606 | Instruction dispatch queue for improved instruction cache to queue timing | Oct 7, 1996 | Issued |
Array
(
[id] => 3796669
[patent_doc_number] => 05819060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Instruction swapping in dual pipeline microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/728411
[patent_app_country] => US
[patent_app_date] => 1996-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2647
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/819/05819060.pdf
[firstpage_image] =>[orig_patent_app_number] => 728411
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/728411 | Instruction swapping in dual pipeline microprocessor | Oct 7, 1996 | Issued |
Array
(
[id] => 4031105
[patent_doc_number] => 05881257
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Data processing system register control'
[patent_app_type] => 1
[patent_app_number] => 8/727312
[patent_app_country] => US
[patent_app_date] => 1996-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 21306
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/881/05881257.pdf
[firstpage_image] =>[orig_patent_app_number] => 727312
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/727312 | Data processing system register control | Oct 7, 1996 | Issued |
Array
(
[id] => 3932994
[patent_doc_number] => 06003127
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Pipeline processing apparatus for reducing delays in the performance of processing operations'
[patent_app_type] => 1
[patent_app_number] => 8/725709
[patent_app_country] => US
[patent_app_date] => 1996-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 3578
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/003/06003127.pdf
[firstpage_image] =>[orig_patent_app_number] => 725709
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/725709 | Pipeline processing apparatus for reducing delays in the performance of processing operations | Oct 3, 1996 | Issued |
Array
(
[id] => 3774679
[patent_doc_number] => 05844830
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Executing computer instrucrions by circuits having different latencies'
[patent_app_type] => 1
[patent_app_number] => 8/719115
[patent_app_country] => US
[patent_app_date] => 1996-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 7925
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/844/05844830.pdf
[firstpage_image] =>[orig_patent_app_number] => 719115
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/719115 | Executing computer instrucrions by circuits having different latencies | Sep 23, 1996 | Issued |
Array
(
[id] => 3894616
[patent_doc_number] => 05799162
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Program counter update mechanism'
[patent_app_type] => 1
[patent_app_number] => 8/716764
[patent_app_country] => US
[patent_app_date] => 1996-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 10361
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 297
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/799/05799162.pdf
[firstpage_image] =>[orig_patent_app_number] => 716764
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/716764 | Program counter update mechanism | Sep 22, 1996 | Issued |
| 08/714518 | INTRODUCTION SEQUENCER FOR NETWORK STRUCTURE MICROPROCESSOR | Sep 15, 1996 | Abandoned |
Array
(
[id] => 3803076
[patent_doc_number] => 05822586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Entity management system with remote call feature'
[patent_app_type] => 1
[patent_app_number] => 8/707357
[patent_app_country] => US
[patent_app_date] => 1996-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6911
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822586.pdf
[firstpage_image] =>[orig_patent_app_number] => 707357
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/707357 | Entity management system with remote call feature | Sep 3, 1996 | Issued |