Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4017978 [patent_doc_number] => 05859993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Dual ROM microprogrammable microprocessor and universal serial bus microcontroller development system' [patent_app_type] => 1 [patent_app_number] => 8/705807 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6311 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859993.pdf [firstpage_image] =>[orig_patent_app_number] => 705807 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705807
Dual ROM microprogrammable microprocessor and universal serial bus microcontroller development system Aug 29, 1996 Issued
Array ( [id] => 4008128 [patent_doc_number] => 05920701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Scheduling data transmission' [patent_app_type] => 1 [patent_app_number] => 8/704115 [patent_app_country] => US [patent_app_date] => 1996-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 7 [patent_no_of_words] => 9006 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920701.pdf [firstpage_image] =>[orig_patent_app_number] => 704115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/704115
Scheduling data transmission Aug 27, 1996 Issued
Array ( [id] => 3915552 [patent_doc_number] => 05944818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method and apparatus for accelerated instruction restart in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/672409 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3364 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944818.pdf [firstpage_image] =>[orig_patent_app_number] => 672409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672409
Method and apparatus for accelerated instruction restart in a microprocessor Jun 27, 1996 Issued
Array ( [id] => 3782547 [patent_doc_number] => 05850523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Method and system for monitoring fieldbus network with multiple packet filters' [patent_app_type] => 1 [patent_app_number] => 8/666116 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5341 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850523.pdf [firstpage_image] =>[orig_patent_app_number] => 666116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/666116
Method and system for monitoring fieldbus network with multiple packet filters Jun 20, 1996 Issued
Array ( [id] => 3813398 [patent_doc_number] => 05828874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Past-history filtered branch prediction' [patent_app_type] => 1 [patent_app_number] => 8/626868 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 31358 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828874.pdf [firstpage_image] =>[orig_patent_app_number] => 626868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626868
Past-history filtered branch prediction Jun 4, 1996 Issued
Array ( [id] => 3758156 [patent_doc_number] => 05754790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Apparatus and method for selecting improved routing paths in an autonomous system of computer networks' [patent_app_type] => 1 [patent_app_number] => 8/641506 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4023 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754790.pdf [firstpage_image] =>[orig_patent_app_number] => 641506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641506
Apparatus and method for selecting improved routing paths in an autonomous system of computer networks Apr 30, 1996 Issued
Array ( [id] => 3802937 [patent_doc_number] => 05822577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Context oriented branch history table' [patent_app_type] => 1 [patent_app_number] => 8/641610 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7554 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822577.pdf [firstpage_image] =>[orig_patent_app_number] => 641610 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641610
Context oriented branch history table Apr 30, 1996 Issued
Array ( [id] => 3661391 [patent_doc_number] => 05606670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system' [patent_app_type] => 1 [patent_app_number] => 8/636173 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6859 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606670.pdf [firstpage_image] =>[orig_patent_app_number] => 636173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636173
Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system Apr 21, 1996 Issued
Array ( [id] => 3836645 [patent_doc_number] => 05790846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Interrupt vectoring for instruction address breakpoint facility in computer systems' [patent_app_type] => 1 [patent_app_number] => 8/634712 [patent_app_country] => US [patent_app_date] => 1996-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5143 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790846.pdf [firstpage_image] =>[orig_patent_app_number] => 634712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634712
Interrupt vectoring for instruction address breakpoint facility in computer systems Apr 17, 1996 Issued
Array ( [id] => 4063697 [patent_doc_number] => 05964863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Method and apparatus for providing pipe fullness information external to a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/632208 [patent_app_country] => US [patent_app_date] => 1996-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2994 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964863.pdf [firstpage_image] =>[orig_patent_app_number] => 632208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/632208
Method and apparatus for providing pipe fullness information external to a data processing system Apr 14, 1996 Issued
Array ( [id] => 3902933 [patent_doc_number] => 05724563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Pipeline processsor' [patent_app_type] => 1 [patent_app_number] => 8/629216 [patent_app_country] => US [patent_app_date] => 1996-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 7865 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724563.pdf [firstpage_image] =>[orig_patent_app_number] => 629216 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629216
Pipeline processsor Apr 7, 1996 Issued
Array ( [id] => 3951807 [patent_doc_number] => 05872948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Processor and method for out-of-order execution of instructions based upon an instruction parameter' [patent_app_type] => 1 [patent_app_number] => 8/616613 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3883 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872948.pdf [firstpage_image] =>[orig_patent_app_number] => 616613 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616613
Processor and method for out-of-order execution of instructions based upon an instruction parameter Mar 14, 1996 Issued
Array ( [id] => 3847967 [patent_doc_number] => 05740391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Preventing premature early exception signaling with special instruction encoding' [patent_app_type] => 1 [patent_app_number] => 8/609207 [patent_app_country] => US [patent_app_date] => 1996-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4479 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740391.pdf [firstpage_image] =>[orig_patent_app_number] => 609207 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/609207
Preventing premature early exception signaling with special instruction encoding Feb 29, 1996 Issued
08/600319 DATA PROCESSOR ALLOWING MULTIFUNCTIONAL INSTRUCTION EXECUTION Feb 12, 1996 Abandoned
08/589425 EMULATION DEVICES, SYSTEMS AND METHODS WITH DISTRIBUTED CONTROL OF CLOCK SELECTION IN CLOCK DOMAINS Jan 21, 1996 Abandoned
Array ( [id] => 3700811 [patent_doc_number] => 05664117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer' [patent_app_type] => 1 [patent_app_number] => 8/603688 [patent_app_country] => US [patent_app_date] => 1996-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9695 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664117.pdf [firstpage_image] =>[orig_patent_app_number] => 603688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/603688
Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer Jan 19, 1996 Issued
08/591233 METHOD AND APPARATUS FOR A BRANCH INSTRUCTION POINTER TABLE Jan 17, 1996 Abandoned
Array ( [id] => 3847981 [patent_doc_number] => 05740392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus for fast decoding of 00H and OFH mapped instructions' [patent_app_type] => 1 [patent_app_number] => 8/579419 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6537 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740392.pdf [firstpage_image] =>[orig_patent_app_number] => 579419 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579419
Method and apparatus for fast decoding of 00H and OFH mapped instructions Dec 26, 1995 Issued
Array ( [id] => 3707819 [patent_doc_number] => 05596734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Method and apparatus for programming embedded memories of a variety of integrated circuits using the IEEE test access port' [patent_app_type] => 1 [patent_app_number] => 8/575178 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4055 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596734.pdf [firstpage_image] =>[orig_patent_app_number] => 575178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575178
Method and apparatus for programming embedded memories of a variety of integrated circuits using the IEEE test access port Dec 18, 1995 Issued
Array ( [id] => 3794238 [patent_doc_number] => 05809272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Early instruction-length pre-decode of variable-length instructions in a superscalar processor' [patent_app_type] => 1 [patent_app_number] => 8/564718 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5419 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809272.pdf [firstpage_image] =>[orig_patent_app_number] => 564718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/564718
Early instruction-length pre-decode of variable-length instructions in a superscalar processor Nov 28, 1995 Issued
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