Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3871432 [patent_doc_number] => 05706490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of processing conditional branch instructions in scalar/vector processor' [patent_app_type] => 1 [patent_app_number] => 8/484103 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 20657 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706490.pdf [firstpage_image] =>[orig_patent_app_number] => 484103 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/484103
Method of processing conditional branch instructions in scalar/vector processor Jun 6, 1995 Issued
Array ( [id] => 3667663 [patent_doc_number] => 05623650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method of processing a sequence of conditional vector IF statements' [patent_app_type] => 1 [patent_app_number] => 8/484124 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 22275 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623650.pdf [firstpage_image] =>[orig_patent_app_number] => 484124 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/484124
Method of processing a sequence of conditional vector IF statements Jun 6, 1995 Issued
Array ( [id] => 3702257 [patent_doc_number] => 05604915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Data processing system having load dependent bus timing' [patent_app_type] => 1 [patent_app_number] => 8/485031 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 17379 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604915.pdf [firstpage_image] =>[orig_patent_app_number] => 485031 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/485031
Data processing system having load dependent bus timing Jun 6, 1995 Issued
08/475400 PARALLEL AND SCALABLE INSTRUCTION SCANNING UNIT Jun 6, 1995 Abandoned
Array ( [id] => 1549855 [patent_doc_number] => 06374389 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method for correcting single bit hard errors' [patent_app_type] => B1 [patent_app_number] => 08/482924 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 209 [patent_no_of_words] => 43283 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374389.pdf [firstpage_image] =>[orig_patent_app_number] => 08482924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/482924
Method for correcting single bit hard errors Jun 6, 1995 Issued
Array ( [id] => 3669856 [patent_doc_number] => 05659706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Vector/scalar processor with simultaneous processing and instruction cache filling' [patent_app_type] => 1 [patent_app_number] => 8/486612 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 22279 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659706.pdf [firstpage_image] =>[orig_patent_app_number] => 486612 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486612
Vector/scalar processor with simultaneous processing and instruction cache filling Jun 6, 1995 Issued
Array ( [id] => 1401380 [patent_doc_number] => 06564314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Computer instruction compression' [patent_app_type] => B1 [patent_app_number] => 08/472515 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564314.pdf [firstpage_image] =>[orig_patent_app_number] => 08472515 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472515
Computer instruction compression Jun 6, 1995 Issued
08/484230 HIGH PERFORMANCE, LOW COST MICROPROCESSOR Jun 6, 1995 Abandoned
Array ( [id] => 3676698 [patent_doc_number] => 05598547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Vector processor having functional unit paths of differing pipeline lengths' [patent_app_type] => 1 [patent_app_number] => 8/478815 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 20987 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598547.pdf [firstpage_image] =>[orig_patent_app_number] => 478815 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/478815
Vector processor having functional unit paths of differing pipeline lengths Jun 6, 1995 Issued
Array ( [id] => 3556477 [patent_doc_number] => 05555402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'A disk storage subsystem for interfacing with a parallel path, a nonvolatile media and a volatile storage medium' [patent_app_type] => 1 [patent_app_number] => 8/486177 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 191 [patent_no_of_words] => 42718 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555402.pdf [firstpage_image] =>[orig_patent_app_number] => 486177 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486177
A disk storage subsystem for interfacing with a parallel path, a nonvolatile media and a volatile storage medium Jun 5, 1995 Issued
Array ( [id] => 3828808 [patent_doc_number] => 05771368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers' [patent_app_type] => 1 [patent_app_number] => 8/449258 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2870 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771368.pdf [firstpage_image] =>[orig_patent_app_number] => 449258 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/449258
Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers May 23, 1995 Issued
08/447770 MICROPROCESSOR WITH MULTIPLE BUS CONFIGURATIONS May 22, 1995 Abandoned
Array ( [id] => 3521604 [patent_doc_number] => 05588126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system' [patent_app_type] => 1 [patent_app_number] => 8/446030 [patent_app_country] => US [patent_app_date] => 1995-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6802 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588126.pdf [firstpage_image] =>[orig_patent_app_number] => 446030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/446030
Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system May 18, 1995 Issued
Array ( [id] => 3660818 [patent_doc_number] => 05638524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Digital signal processor and method for executing DSP and RISC class instructions defining identical data processing or data transfer operations' [patent_app_type] => 1 [patent_app_number] => 8/443199 [patent_app_country] => US [patent_app_date] => 1995-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 33065 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638524.pdf [firstpage_image] =>[orig_patent_app_number] => 443199 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/443199
Digital signal processor and method for executing DSP and RISC class instructions defining identical data processing or data transfer operations May 16, 1995 Issued
Array ( [id] => 3659669 [patent_doc_number] => 05630074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Inter-program communication and scheduling method for personal computers' [patent_app_type] => 1 [patent_app_number] => 8/441120 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 9354 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630074.pdf [firstpage_image] =>[orig_patent_app_number] => 441120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/441120
Inter-program communication and scheduling method for personal computers May 14, 1995 Issued
Array ( [id] => 3511202 [patent_doc_number] => 05533203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Start of packet receive interrupt for ethernet controller' [patent_app_type] => 1 [patent_app_number] => 8/437068 [patent_app_country] => US [patent_app_date] => 1995-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/533/05533203.pdf [firstpage_image] =>[orig_patent_app_number] => 437068 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/437068
Start of packet receive interrupt for ethernet controller May 8, 1995 Issued
Array ( [id] => 3552550 [patent_doc_number] => 05481686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Floating-point processor with apparent-precision based selection of execution-precision' [patent_app_type] => 1 [patent_app_number] => 8/433829 [patent_app_country] => US [patent_app_date] => 1995-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3389 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481686.pdf [firstpage_image] =>[orig_patent_app_number] => 433829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/433829
Floating-point processor with apparent-precision based selection of execution-precision May 3, 1995 Issued
Array ( [id] => 3701472 [patent_doc_number] => 05692170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Apparatus for detecting and executing traps in a superscalar processor' [patent_app_type] => 1 [patent_app_number] => 8/431219 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5446 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692170.pdf [firstpage_image] =>[orig_patent_app_number] => 431219 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/431219
Apparatus for detecting and executing traps in a superscalar processor Apr 27, 1995 Issued
Array ( [id] => 3642383 [patent_doc_number] => 05687360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Branch predictor using multiple prediction heuristics and a heuristic identifier in the branch instruction' [patent_app_type] => 1 [patent_app_number] => 8/431016 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6393 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687360.pdf [firstpage_image] =>[orig_patent_app_number] => 431016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/431016
Branch predictor using multiple prediction heuristics and a heuristic identifier in the branch instruction Apr 27, 1995 Issued
Array ( [id] => 3794964 [patent_doc_number] => 05809320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'High-performance multi-processor having floating point unit' [patent_app_type] => 1 [patent_app_number] => 8/415771 [patent_app_country] => US [patent_app_date] => 1995-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 45294 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809320.pdf [firstpage_image] =>[orig_patent_app_number] => 415771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/415771
High-performance multi-processor having floating point unit Apr 2, 1995 Issued
Menu