Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3526331 [patent_doc_number] => 05513331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset' [patent_app_type] => 1 [patent_app_number] => 8/412607 [patent_app_country] => US [patent_app_date] => 1995-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8653 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513331.pdf [firstpage_image] =>[orig_patent_app_number] => 412607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/412607
Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset Mar 28, 1995 Issued
08/404942 COMPUTER SYSTEM HAVING A DIGITAL SIGNAL PROCESSOR FOR PERFORMING AUDIO FUNCTIONS AND AN OPTION CARD FOR CONNECTION TO SAID DIGITAL SIGNAL PROCESSOR FOR PERFORMING MODEM AND FAX FUNCTIONS Mar 14, 1995 Abandoned
Array ( [id] => 3745576 [patent_doc_number] => 05694588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Apparatus and method for synchronizing data transfers in a single instruction multiple data processor' [patent_app_type] => 1 [patent_app_number] => 8/403541 [patent_app_country] => US [patent_app_date] => 1995-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 12631 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694588.pdf [firstpage_image] =>[orig_patent_app_number] => 403541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403541
Apparatus and method for synchronizing data transfers in a single instruction multiple data processor Mar 13, 1995 Issued
Array ( [id] => 3595567 [patent_doc_number] => 05581719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Multiple block line prediction' [patent_app_type] => 1 [patent_app_number] => 8/401656 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 31513 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581719.pdf [firstpage_image] =>[orig_patent_app_number] => 401656 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401656
Multiple block line prediction Mar 9, 1995 Issued
Array ( [id] => 3758362 [patent_doc_number] => 05754805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Instruction in a data processing system utilizing extension bits and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/401610 [patent_app_country] => US [patent_app_date] => 1995-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 196 [patent_figures_cnt] => 318 [patent_no_of_words] => 76864 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754805.pdf [firstpage_image] =>[orig_patent_app_number] => 401610 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401610
Instruction in a data processing system utilizing extension bits and method therefor Mar 8, 1995 Issued
Array ( [id] => 3566408 [patent_doc_number] => 05574892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Use of between-instruction breaks to implement complex in-circuit emulation features' [patent_app_type] => 1 [patent_app_number] => 8/396278 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4850 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574892.pdf [firstpage_image] =>[orig_patent_app_number] => 396278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/396278
Use of between-instruction breaks to implement complex in-circuit emulation features Feb 27, 1995 Issued
Array ( [id] => 3660223 [patent_doc_number] => 05640524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Method and apparatus for chaining vector instructions' [patent_app_type] => 1 [patent_app_number] => 8/395320 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 20892 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640524.pdf [firstpage_image] =>[orig_patent_app_number] => 395320 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/395320
Method and apparatus for chaining vector instructions Feb 27, 1995 Issued
Array ( [id] => 3667755 [patent_doc_number] => 05623657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'System for processing application programs including a language independent context management technique' [patent_app_type] => 1 [patent_app_number] => 8/396368 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3321 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623657.pdf [firstpage_image] =>[orig_patent_app_number] => 396368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/396368
System for processing application programs including a language independent context management technique Feb 27, 1995 Issued
08/395008 INSTRUCTION SET AND EXECUTING METHOD OF THE SAME BY MICROCOMPUTER Feb 26, 1995 Abandoned
Array ( [id] => 3616412 [patent_doc_number] => 05579494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Apparatus for detecting possibility of parallel processing and method thereof and a program translation apparatus utilized therein' [patent_app_type] => 1 [patent_app_number] => 8/395373 [patent_app_country] => US [patent_app_date] => 1995-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9314 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579494.pdf [firstpage_image] =>[orig_patent_app_number] => 395373 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/395373
Apparatus for detecting possibility of parallel processing and method thereof and a program translation apparatus utilized therein Feb 20, 1995 Issued
Array ( [id] => 3466870 [patent_doc_number] => 05452433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Common agent computer management system and method' [patent_app_type] => 1 [patent_app_number] => 8/386610 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5175 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452433.pdf [firstpage_image] =>[orig_patent_app_number] => 386610 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386610
Common agent computer management system and method Feb 9, 1995 Issued
Array ( [id] => 3744307 [patent_doc_number] => 05666549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method and system for processing a document transmitted via facsimile in an initially input form stored in a knowledge base' [patent_app_type] => 1 [patent_app_number] => 8/386182 [patent_app_country] => US [patent_app_date] => 1995-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 6005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666549.pdf [firstpage_image] =>[orig_patent_app_number] => 386182 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386182
Method and system for processing a document transmitted via facsimile in an initially input form stored in a knowledge base Feb 8, 1995 Issued
Array ( [id] => 3633972 [patent_doc_number] => 05689653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Vector memory operations' [patent_app_type] => 1 [patent_app_number] => 8/384308 [patent_app_country] => US [patent_app_date] => 1995-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 7390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689653.pdf [firstpage_image] =>[orig_patent_app_number] => 384308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/384308
Vector memory operations Feb 5, 1995 Issued
Array ( [id] => 3589386 [patent_doc_number] => 05524255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method and apparatus for accessing global registers in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/379123 [patent_app_country] => US [patent_app_date] => 1995-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6733 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524255.pdf [firstpage_image] =>[orig_patent_app_number] => 379123 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/379123
Method and apparatus for accessing global registers in a multiprocessor system Jan 26, 1995 Issued
08/377813 DISTRIBUTED COMPLETION CONTROL IN A MICROPROCESSOR Jan 24, 1995 Abandoned
Array ( [id] => 3592935 [patent_doc_number] => 05499382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Circuit and method of bit-packing and bit-unpacking using a barrel shifter' [patent_app_type] => 1 [patent_app_number] => 8/376635 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12182 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499382.pdf [firstpage_image] =>[orig_patent_app_number] => 376635 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/376635
Circuit and method of bit-packing and bit-unpacking using a barrel shifter Jan 22, 1995 Issued
08/376915 CLEAR PROCESSING OF A TRANSLATION LOOKASIDE BUFFER WITH LESS WAITING TIME Jan 22, 1995 Abandoned
Array ( [id] => 3701126 [patent_doc_number] => 05644759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Apparatus and method for processing a jump instruction preceded by a skip instruction' [patent_app_type] => 1 [patent_app_number] => 8/375219 [patent_app_country] => US [patent_app_date] => 1995-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4876 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644759.pdf [firstpage_image] =>[orig_patent_app_number] => 375219 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375219
Apparatus and method for processing a jump instruction preceded by a skip instruction Jan 18, 1995 Issued
Array ( [id] => 3870945 [patent_doc_number] => 05706459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Processor having a variable number of stages in a pipeline' [patent_app_type] => 1 [patent_app_number] => 8/367494 [patent_app_country] => US [patent_app_date] => 1994-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 42 [patent_no_of_words] => 20541 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706459.pdf [firstpage_image] =>[orig_patent_app_number] => 367494 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/367494
Processor having a variable number of stages in a pipeline Dec 29, 1994 Issued
08/359005 INTRODUCTION SEQUENCER FOR NETWORK STRUCTURE MICROPROCESSOR Dec 18, 1994 Abandoned
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