Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3494963 [patent_doc_number] => 05446850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Cross-cache-line compounding algorithm for scism processors' [patent_app_type] => 1 [patent_app_number] => 8/281321 [patent_app_country] => US [patent_app_date] => 1994-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6365 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446850.pdf [firstpage_image] =>[orig_patent_app_number] => 281321 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/281321
Cross-cache-line compounding algorithm for scism processors Jul 26, 1994 Issued
08/272207 MEDIATED ACCESS TO AN INTELLIGENT NETWORK Jul 7, 1994 Abandoned
Array ( [id] => 3556122 [patent_doc_number] => 05555379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Cache controller index address generator' [patent_app_type] => 1 [patent_app_number] => 8/271105 [patent_app_country] => US [patent_app_date] => 1994-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4943 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555379.pdf [firstpage_image] =>[orig_patent_app_number] => 271105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/271105
Cache controller index address generator Jul 5, 1994 Issued
Array ( [id] => 3910142 [patent_doc_number] => 05835743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Application binary interface and method of interfacing binary application program to digital computer' [patent_app_type] => 1 [patent_app_number] => 8/269035 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 12458 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835743.pdf [firstpage_image] =>[orig_patent_app_number] => 269035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269035
Application binary interface and method of interfacing binary application program to digital computer Jun 29, 1994 Issued
Array ( [id] => 3521547 [patent_doc_number] => 05588122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Universal buffered interface for coupling multiple processors memory units, and I/O interfaces to a common high-speed interconnect' [patent_app_type] => 1 [patent_app_number] => 8/260107 [patent_app_country] => US [patent_app_date] => 1994-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 40 [patent_no_of_words] => 19930 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588122.pdf [firstpage_image] =>[orig_patent_app_number] => 260107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/260107
Universal buffered interface for coupling multiple processors memory units, and I/O interfaces to a common high-speed interconnect Jun 14, 1994 Issued
Array ( [id] => 3873170 [patent_doc_number] => 05768613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Computing apparatus configured for partitioned processing' [patent_app_type] => 1 [patent_app_number] => 8/255566 [patent_app_country] => US [patent_app_date] => 1994-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 11479 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768613.pdf [firstpage_image] =>[orig_patent_app_number] => 255566 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/255566
Computing apparatus configured for partitioned processing Jun 7, 1994 Issued
Array ( [id] => 3502085 [patent_doc_number] => 05471636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Software development system and method of using same' [patent_app_type] => 1 [patent_app_number] => 8/254156 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4601 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471636.pdf [firstpage_image] =>[orig_patent_app_number] => 254156 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/254156
Software development system and method of using same Jun 5, 1994 Issued
Array ( [id] => 3707792 [patent_doc_number] => 05596732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Method of optimizing instruction sequence of compiler' [patent_app_type] => 1 [patent_app_number] => 8/253138 [patent_app_country] => US [patent_app_date] => 1994-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 8099 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596732.pdf [firstpage_image] =>[orig_patent_app_number] => 253138 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/253138
Method of optimizing instruction sequence of compiler Jun 1, 1994 Issued
Array ( [id] => 3674319 [patent_doc_number] => 05649225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Resynchronization of a superscalar processor' [patent_app_type] => 1 [patent_app_number] => 8/252308 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 22348 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649225.pdf [firstpage_image] =>[orig_patent_app_number] => 252308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252308
Resynchronization of a superscalar processor May 31, 1994 Issued
Array ( [id] => 3612175 [patent_doc_number] => 05559975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Program counter update mechanism' [patent_app_type] => 1 [patent_app_number] => 8/252030 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10333 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559975.pdf [firstpage_image] =>[orig_patent_app_number] => 252030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/252030
Program counter update mechanism May 31, 1994 Issued
Array ( [id] => 3127769 [patent_doc_number] => 05396611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Microprocessor use in in-circuit emulator having function of discriminating user\'s space and in-circuit emulator space' [patent_app_type] => 1 [patent_app_number] => 8/251020 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3327 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396611.pdf [firstpage_image] =>[orig_patent_app_number] => 251020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251020
Microprocessor use in in-circuit emulator having function of discriminating user's space and in-circuit emulator space May 30, 1994 Issued
08/250519 COMMUNICATIONS SYSTEM USABLE AS SYSTEM FOR SIMULATING A PLURALITY OF OTHER COMMUNICATIONS SYSTEMS AND COMMUNICATION PROCESSING SYSTEM HAVING SUCH COMMUNICATIONS SYSTEM May 26, 1994 Abandoned
Array ( [id] => 3500387 [patent_doc_number] => 05475818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Communications controller central processing unit board' [patent_app_type] => 1 [patent_app_number] => 8/250866 [patent_app_country] => US [patent_app_date] => 1994-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 7322 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475818.pdf [firstpage_image] =>[orig_patent_app_number] => 250866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/250866
Communications controller central processing unit board May 25, 1994 Issued
Array ( [id] => 3133749 [patent_doc_number] => 05381536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Method and apparatus for separate mark and wait instructions for processors having multiple memory ports' [patent_app_type] => 1 [patent_app_number] => 8/249084 [patent_app_country] => US [patent_app_date] => 1994-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2676 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381536.pdf [firstpage_image] =>[orig_patent_app_number] => 249084 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/249084
Method and apparatus for separate mark and wait instructions for processors having multiple memory ports May 24, 1994 Issued
Array ( [id] => 3600990 [patent_doc_number] => 05550994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Condition decision circuit for a microcomputer' [patent_app_type] => 1 [patent_app_number] => 8/247836 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 73 [patent_no_of_words] => 18238 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550994.pdf [firstpage_image] =>[orig_patent_app_number] => 247836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247836
Condition decision circuit for a microcomputer May 22, 1994 Issued
08/245886 DATA PROCESSOR ALLOWING MUTLI-FUNCTIONAL INSTRUCTION EXECUTION May 15, 1994 Abandoned
08/241108 FLOATING-POINT PROCESSOR WITH APPARENT-PRECISION BASED SELECTION OF EXECUTION-PRECISION May 10, 1994 Abandoned
08/240602 HIGH-PERFORMANCE MULTI-PROCESSOR HAVING FLOATING POINT UNIT May 9, 1994 Abandoned
Array ( [id] => 3627077 [patent_doc_number] => 05535408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Processor chip for parallel processing system' [patent_app_type] => 1 [patent_app_number] => 8/237981 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 27373 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535408.pdf [firstpage_image] =>[orig_patent_app_number] => 237981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237981
Processor chip for parallel processing system May 1, 1994 Issued
Array ( [id] => 3500580 [patent_doc_number] => 05475832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Logic simulation method' [patent_app_type] => 1 [patent_app_number] => 8/233981 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 41 [patent_no_of_words] => 9613 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475832.pdf [firstpage_image] =>[orig_patent_app_number] => 233981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/233981
Logic simulation method Apr 27, 1994 Issued
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