Raj R. Gupta

Array ( [id] => 3083098 [patent_doc_number] => 05361389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Apparatus and method for emulation routine instruction issue' [patent_app_type] => 1 [patent_app_number] => 8/127254 [patent_app_country] => US [patent_app_date] => 1993-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12513 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361389.pdf [firstpage_image] =>[orig_patent_app_number] => 127254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495131 [patent_doc_number] => 05446861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Variable data rate improvement of disc cache subsystem' [patent_app_type] => 1 [patent_app_number] => 8/112401 [patent_app_country] => US [patent_app_date] => 1993-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9563 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446861.pdf [firstpage_image] =>[orig_patent_app_number] => 112401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3094882 [patent_doc_number] => 05280593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Computer system permitting switching between architected and interpretation instructions in a pipeline by enabling pipeline drain' [patent_app_type] => 1 [patent_app_number] => 8/098760 [patent_app_country] => US [patent_app_date] => 1993-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10433 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280593.pdf [firstpage_image] =>[orig_patent_app_number] => 098760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3895013 [patent_doc_number] => 05799189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Computer system with downward compatibility function' [patent_app_type] => 1 [patent_app_number] => 8/095033 [patent_app_country] => US [patent_app_date] => 1993-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4379 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799189.pdf [firstpage_image] =>[orig_patent_app_number] => 095033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3063680 [patent_doc_number] => 05305463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Null convention logic system' [patent_app_type] => 1 [patent_app_number] => 8/074288 [patent_app_country] => US [patent_app_date] => 1993-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 76 [patent_no_of_words] => 37657 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305463.pdf [firstpage_image] =>[orig_patent_app_number] => 074288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3117678 [patent_doc_number] => 05448705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'RISC microprocessor architecture implementing fast trap and exception state' [patent_app_type] => 1 [patent_app_number] => 8/065063 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 31422 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448705.pdf [firstpage_image] =>[orig_patent_app_number] => 065063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3467403 [patent_doc_number] => 05452467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Microcomputer with high density ram in separate isolation well on single chip' [patent_app_type] => 1 [patent_app_number] => 8/066462 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 20840 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452467.pdf [firstpage_image] =>[orig_patent_app_number] => 066462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3600709 [patent_doc_number] => 05550977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Multi-media mailing method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/063928 [patent_app_country] => US [patent_app_date] => 1993-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 10577 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550977.pdf [firstpage_image] =>[orig_patent_app_number] => 063928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3107147 [patent_doc_number] => 05369776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-29 [patent_title] => 'Apparatus for producing slips of variable length and having pre-stored word names, and wherein labels are added to word data thereon' [patent_app_type] => 1 [patent_app_number] => 8/060211 [patent_app_country] => US [patent_app_date] => 1993-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 8676 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/369/05369776.pdf [firstpage_image] =>[orig_patent_app_number] => 060211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3486509 [patent_doc_number] => 05428749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Event signalling system and method for processor system having central memory unit' [patent_app_type] => 1 [patent_app_number] => 8/059510 [patent_app_country] => US [patent_app_date] => 1993-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7028 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428749.pdf [firstpage_image] =>[orig_patent_app_number] => 059510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2977632 [patent_doc_number] => 05274826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Transparent system interrupts with automated input/output trap restart' [patent_app_type] => 1 [patent_app_number] => 8/053960 [patent_app_country] => US [patent_app_date] => 1993-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2868 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 496 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274826.pdf [firstpage_image] =>[orig_patent_app_number] => 053960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3134137 [patent_doc_number] => 05381556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Semiconductor device having externally programmable memory' [patent_app_type] => 1 [patent_app_number] => 8/048410 [patent_app_country] => US [patent_app_date] => 1993-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9207 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381556.pdf [firstpage_image] =>[orig_patent_app_number] => 048410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3438899 [patent_doc_number] => 05455911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Communications protocol for use in transferring data over a serial bus' [patent_app_type] => 1 [patent_app_number] => 8/043170 [patent_app_country] => US [patent_app_date] => 1993-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 6254 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455911.pdf [firstpage_image] =>[orig_patent_app_number] => 043170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3460989 [patent_doc_number] => 05386582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'High speed time base counter in a field programmable gate array (FPGA)' [patent_app_type] => 1 [patent_app_number] => 8/030802 [patent_app_country] => US [patent_app_date] => 1993-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1451 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386582.pdf [firstpage_image] =>[orig_patent_app_number] => 030802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3469129 [patent_doc_number] => 05383196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'SONET signal generating apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/029981 [patent_app_country] => US [patent_app_date] => 1993-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6955 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/383/05383196.pdf [firstpage_image] =>[orig_patent_app_number] => 029981 [rel_patent_id] =>[rel_patent_doc_number] =>)