| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3064932
[patent_doc_number] => 05307478
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'Method for inserting a path instruction during compliation of computer programs for processors having multiple functional units'
[patent_app_type] => 1
[patent_app_number] => 7/969789
[patent_app_country] => US
[patent_app_date] => 1992-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6338
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/307/05307478.pdf
[firstpage_image] =>[orig_patent_app_number] => 969789
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/969789 | Method for inserting a path instruction during compliation of computer programs for processors having multiple functional units | Oct 28, 1992 | Issued |
Array
(
[id] => 3437605
[patent_doc_number] => 05404462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Dual bus interface transfer system for central processing module'
[patent_app_type] => 1
[patent_app_number] => 7/963304
[patent_app_country] => US
[patent_app_date] => 1992-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 24
[patent_no_of_words] => 17903
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404462.pdf
[firstpage_image] =>[orig_patent_app_number] => 963304
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/963304 | Dual bus interface transfer system for central processing module | Oct 15, 1992 | Issued |
Array
(
[id] => 3128537
[patent_doc_number] => 05410658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-25
[patent_title] => 'Microprocessor for carrying out a plurality of different microprograms at the same time and method for controlling the microprocessor'
[patent_app_type] => 1
[patent_app_number] => 7/960505
[patent_app_country] => US
[patent_app_date] => 1992-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4698
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/410/05410658.pdf
[firstpage_image] =>[orig_patent_app_number] => 960505
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/960505 | Microprocessor for carrying out a plurality of different microprograms at the same time and method for controlling the microprocessor | Oct 12, 1992 | Issued |
| 07/957745 | METHOD AND APPARATUS FOR THE DIRECT TRANSFER OF INFORMATION BETWEEN APPLICATION PROGRAMS RUNNING ON THE DISTINCT PROCESSORS WITHOUT UTILIZING THE SERVICES OF ONE OR BOTH OPERATING SYSTEMS | Oct 6, 1992 | Abandoned |
Array
(
[id] => 3427122
[patent_doc_number] => 05454098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-26
[patent_title] => 'Method of emulating access to a sequential access data storage device while actually using a random access storage device'
[patent_app_type] => 1
[patent_app_number] => 7/951602
[patent_app_country] => US
[patent_app_date] => 1992-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 4620
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/454/05454098.pdf
[firstpage_image] =>[orig_patent_app_number] => 951602
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/951602 | Method of emulating access to a sequential access data storage device while actually using a random access storage device | Sep 27, 1992 | Issued |
Array
(
[id] => 3636387
[patent_doc_number] => 05602994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Method and apparatus for high speed data acquisition and processing'
[patent_app_type] => 1
[patent_app_number] => 7/950548
[patent_app_country] => US
[patent_app_date] => 1992-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 7612
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/602/05602994.pdf
[firstpage_image] =>[orig_patent_app_number] => 950548
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/950548 | Method and apparatus for high speed data acquisition and processing | Sep 24, 1992 | Issued |
Array
(
[id] => 3064586
[patent_doc_number] => 05307461
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'Multiple rank hierarchical data storage system with data coherence'
[patent_app_type] => 1
[patent_app_number] => 7/950745
[patent_app_country] => US
[patent_app_date] => 1992-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4708
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/307/05307461.pdf
[firstpage_image] =>[orig_patent_app_number] => 950745
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/950745 | Multiple rank hierarchical data storage system with data coherence | Sep 23, 1992 | Issued |
| 07/934606 | MULTIPLE BLOCK TRANSFER MECHANISM | Aug 23, 1992 | Abandoned |
| 07/928555 | REFRESH CONTROL FOR DYNAMIC MEMORY IN MULTIPLE PROCESSOR SYSTEM | Aug 10, 1992 | Abandoned |
Array
(
[id] => 3079380
[patent_doc_number] => 05353420
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-04
[patent_title] => 'Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor'
[patent_app_type] => 1
[patent_app_number] => 7/927707
[patent_app_country] => US
[patent_app_date] => 1992-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 6616
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/353/05353420.pdf
[firstpage_image] =>[orig_patent_app_number] => 927707
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/927707 | Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor | Aug 9, 1992 | Issued |
| 07/927708 | APPARATUS FOR REGISTER BYPASSING IN A MICROPROCESSOR | Aug 9, 1992 | Abandoned |
| 07/918892 | TWO STAGE CACHE MEMORY SYSTEM AND METHOD | Jul 15, 1992 | Abandoned |
Array
(
[id] => 3041879
[patent_doc_number] => 05349683
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-20
[patent_title] => 'Bidirectional FIFO with parity generator/checker'
[patent_app_type] => 1
[patent_app_number] => 7/916304
[patent_app_country] => US
[patent_app_date] => 1992-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4087
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 549
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/349/05349683.pdf
[firstpage_image] =>[orig_patent_app_number] => 916304
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/916304 | Bidirectional FIFO with parity generator/checker | Jul 15, 1992 | Issued |
| 07/911649 | METHOD AND APPARATUS FOR SEPARATE MEMORY HAZARD MARK AND WAIT INSTRUCTIONS FOR PROCESSORS HAVING MULTIPLE MEMORY PORTS | Jul 9, 1992 | Abandoned |
Array
(
[id] => 3495697
[patent_doc_number] => 05446899
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-29
[patent_title] => 'Hint generation in smart recompilation'
[patent_app_type] => 1
[patent_app_number] => 7/906212
[patent_app_country] => US
[patent_app_date] => 1992-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 30
[patent_no_of_words] => 10866
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/446/05446899.pdf
[firstpage_image] =>[orig_patent_app_number] => 906212
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/906212 | Hint generation in smart recompilation | Jun 25, 1992 | Issued |
Array
(
[id] => 3064479
[patent_doc_number] => 05325494
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-28
[patent_title] => 'Computer'
[patent_app_type] => 1
[patent_app_number] => 7/899910
[patent_app_country] => US
[patent_app_date] => 1992-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 11082
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/325/05325494.pdf
[firstpage_image] =>[orig_patent_app_number] => 899910
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/899910 | Computer | Jun 16, 1992 | Issued |
Array
(
[id] => 2980165
[patent_doc_number] => 05202975
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-13
[patent_title] => 'Method for optimizing instruction scheduling for a processor having multiple functional resources'
[patent_app_type] => 1
[patent_app_number] => 7/896895
[patent_app_country] => US
[patent_app_date] => 1992-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6407
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/202/05202975.pdf
[firstpage_image] =>[orig_patent_app_number] => 896895
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/896895 | Method for optimizing instruction scheduling for a processor having multiple functional resources | Jun 9, 1992 | Issued |
Array
(
[id] => 2992708
[patent_doc_number] => 05253358
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-12
[patent_title] => 'Cache memory expansion and transparent interconnection'
[patent_app_type] => 1
[patent_app_number] => 7/883049
[patent_app_country] => US
[patent_app_date] => 1992-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 13923
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 399
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/253/05253358.pdf
[firstpage_image] =>[orig_patent_app_number] => 883049
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/883049 | Cache memory expansion and transparent interconnection | May 6, 1992 | Issued |
| 07/875507 | CROSS-CACHE-LINE COMPOUNDING ALGORITHM FOR SCISM PROCESSORS | Apr 28, 1992 | Abandoned |
Array
(
[id] => 3089860
[patent_doc_number] => 05297264
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Microprogram-controlled device comprising a control storage device with a small storage capacity'
[patent_app_type] => 1
[patent_app_number] => 7/872406
[patent_app_country] => US
[patent_app_date] => 1992-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 7851
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/297/05297264.pdf
[firstpage_image] =>[orig_patent_app_number] => 872406
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/872406 | Microprogram-controlled device comprising a control storage device with a small storage capacity | Apr 22, 1992 | Issued |