| Application number | Title of the application | Filing Date | Status |
|---|
| 07/871204 | FILE MANAGER FOR FILES SHARED BY HETEROGENEOUS CLIENTS | Apr 19, 1992 | Abandoned |
Array
(
[id] => 3058249
[patent_doc_number] => 05287457
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Computer system DMA transfer'
[patent_app_type] => 1
[patent_app_number] => 7/870159
[patent_app_country] => US
[patent_app_date] => 1992-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3222
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 384
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/287/05287457.pdf
[firstpage_image] =>[orig_patent_app_number] => 870159
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/870159 | Computer system DMA transfer | Apr 14, 1992 | Issued |
| 07/865107 | INTERFACE SYSTEM FOR COUPLING TWO COMPUTER ENVIRONMENTS | Apr 7, 1992 | Abandoned |
Array
(
[id] => 3032629
[patent_doc_number] => 05303357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-12
[patent_title] => 'Loop optimization system'
[patent_app_type] => 1
[patent_app_number] => 7/863709
[patent_app_country] => US
[patent_app_date] => 1992-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2492
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/303/05303357.pdf
[firstpage_image] =>[orig_patent_app_number] => 863709
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/863709 | Loop optimization system | Apr 2, 1992 | Issued |
Array
(
[id] => 3067227
[patent_doc_number] => 05345570
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-06
[patent_title] => 'Microprogram control circuit'
[patent_app_type] => 1
[patent_app_number] => 7/862010
[patent_app_country] => US
[patent_app_date] => 1992-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 5887
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/345/05345570.pdf
[firstpage_image] =>[orig_patent_app_number] => 862010
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/862010 | Microprogram control circuit | Mar 31, 1992 | Issued |
Array
(
[id] => 2908248
[patent_doc_number] => 05241666
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Variable rate improvement of disc cache subsystem'
[patent_app_type] => 1
[patent_app_number] => 7/857113
[patent_app_country] => US
[patent_app_date] => 1992-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 9562
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 335
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/241/05241666.pdf
[firstpage_image] =>[orig_patent_app_number] => 857113
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/857113 | Variable rate improvement of disc cache subsystem | Mar 22, 1992 | Issued |
| 07/853402 | COMMUNICATIONS CONTROLLER CENTRAL PROCESSING UNIT BOARD | Mar 17, 1992 | Abandoned |
Array
(
[id] => 2889631
[patent_doc_number] => 05159673
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-27
[patent_title] => 'Apparatus for networking programmable logic controllers to host computers'
[patent_app_type] => 1
[patent_app_number] => 7/850234
[patent_app_country] => US
[patent_app_date] => 1992-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8018
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 417
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/159/05159673.pdf
[firstpage_image] =>[orig_patent_app_number] => 850234
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/850234 | Apparatus for networking programmable logic controllers to host computers | Mar 10, 1992 | Issued |
Array
(
[id] => 2899441
[patent_doc_number] => 05214764
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-25
[patent_title] => 'Data processing apparatus for operating on variable-length data delimited by delimiter codes'
[patent_app_type] => 1
[patent_app_number] => 7/844994
[patent_app_country] => US
[patent_app_date] => 1992-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4996
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/214/05214764.pdf
[firstpage_image] =>[orig_patent_app_number] => 844994
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/844994 | Data processing apparatus for operating on variable-length data delimited by delimiter codes | Mar 1, 1992 | Issued |
Array
(
[id] => 3437692
[patent_doc_number] => 05404469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Multi-threaded microprocessor architecture utilizing static interleaving'
[patent_app_type] => 1
[patent_app_number] => 7/840903
[patent_app_country] => US
[patent_app_date] => 1992-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 5112
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404469.pdf
[firstpage_image] =>[orig_patent_app_number] => 840903
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/840903 | Multi-threaded microprocessor architecture utilizing static interleaving | Feb 24, 1992 | Issued |
Array
(
[id] => 2787572
[patent_doc_number] => 05151980
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-29
[patent_title] => 'Buffer control circuit for data processor'
[patent_app_type] => 1
[patent_app_number] => 7/837607
[patent_app_country] => US
[patent_app_date] => 1992-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3010
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/151/05151980.pdf
[firstpage_image] =>[orig_patent_app_number] => 837607
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/837607 | Buffer control circuit for data processor | Feb 20, 1992 | Issued |
Array
(
[id] => 2817072
[patent_doc_number] => 05146579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-08
[patent_title] => 'Data processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/837602
[patent_app_country] => US
[patent_app_date] => 1992-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1008
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/146/05146579.pdf
[firstpage_image] =>[orig_patent_app_number] => 837602
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/837602 | Data processing apparatus | Feb 20, 1992 | Issued |
Array
(
[id] => 2998892
[patent_doc_number] => 05212795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-18
[patent_title] => 'Programmable DMA controller'
[patent_app_type] => 1
[patent_app_number] => 7/833636
[patent_app_country] => US
[patent_app_date] => 1992-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 13074
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/212/05212795.pdf
[firstpage_image] =>[orig_patent_app_number] => 833636
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/833636 | Programmable DMA controller | Feb 9, 1992 | Issued |
Array
(
[id] => 3122065
[patent_doc_number] => 05408620
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'Circuit for executing conditional branch instructions in pipeline process'
[patent_app_type] => 1
[patent_app_number] => 7/828701
[patent_app_country] => US
[patent_app_date] => 1992-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 6804
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/408/05408620.pdf
[firstpage_image] =>[orig_patent_app_number] => 828701
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/828701 | Circuit for executing conditional branch instructions in pipeline process | Jan 30, 1992 | Issued |
Array
(
[id] => 3012021
[patent_doc_number] => 05359709
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-25
[patent_title] => 'Apparatus and method for providing multiple operating configurations in data circuit terminating equipment'
[patent_app_type] => 1
[patent_app_number] => 7/826504
[patent_app_country] => US
[patent_app_date] => 1992-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6943
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 364
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/359/05359709.pdf
[firstpage_image] =>[orig_patent_app_number] => 826504
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/826504 | Apparatus and method for providing multiple operating configurations in data circuit terminating equipment | Jan 26, 1992 | Issued |
| 07/822703 | MULTI-PROCESSOR SYSTEM IN WHICH AT LEAST TWO PROCESSORS ACCESS THE SAME MEMORY | Jan 20, 1992 | Abandoned |
Array
(
[id] => 3041845
[patent_doc_number] => 05349681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-20
[patent_title] => 'Bit searching circuit and data processor including the same'
[patent_app_type] => 1
[patent_app_number] => 7/821802
[patent_app_country] => US
[patent_app_date] => 1992-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 43
[patent_no_of_words] => 17839
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/349/05349681.pdf
[firstpage_image] =>[orig_patent_app_number] => 821802
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/821802 | Bit searching circuit and data processor including the same | Jan 15, 1992 | Issued |
| 07/819205 | DATA PROCESSOR | Jan 9, 1992 | Abandoned |
| 07/817811 | RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE | Jan 7, 1992 | Abandoned |
| 07/785790 | INSTRUCTION SEQUENCER FOR NETWORK STRUCTURE MICROPROCESSOR | Oct 30, 1991 | Abandoned |