Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3126721 [patent_doc_number] => 05414866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'One-chip microcomputer with parallel operating load and unload data buses' [patent_app_type] => 1 [patent_app_number] => 7/783906 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2709 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414866.pdf [firstpage_image] =>[orig_patent_app_number] => 783906 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/783906
One-chip microcomputer with parallel operating load and unload data buses Oct 28, 1991 Issued
Array ( [id] => 2952271 [patent_doc_number] => 05261115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Multi-board system with shift board selection' [patent_app_type] => 1 [patent_app_number] => 7/781704 [patent_app_country] => US [patent_app_date] => 1991-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6589 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261115.pdf [firstpage_image] =>[orig_patent_app_number] => 781704 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/781704
Multi-board system with shift board selection Oct 21, 1991 Issued
07/766827 COMPUTING APPARATUS CONFIGURED FOR PARTITIONED PROCESSING Sep 26, 1991 Abandoned
Array ( [id] => 3094210 [patent_doc_number] => 05321843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Information retrieval apparatus and information editing system using the same' [patent_app_type] => 1 [patent_app_number] => 7/761905 [patent_app_country] => US [patent_app_date] => 1991-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 17161 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321843.pdf [firstpage_image] =>[orig_patent_app_number] => 761905 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/761905
Information retrieval apparatus and information editing system using the same Sep 11, 1991 Issued
Array ( [id] => 2817625 [patent_doc_number] => 05146607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Method and apparatus for sharing information between a plurality of processing units' [patent_app_type] => 1 [patent_app_number] => 7/758726 [patent_app_country] => US [patent_app_date] => 1991-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6438 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146607.pdf [firstpage_image] =>[orig_patent_app_number] => 758726 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/758726
Method and apparatus for sharing information between a plurality of processing units Sep 8, 1991 Issued
Array ( [id] => 3015431 [patent_doc_number] => 05371855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Disc cache subsystem having plural-level cache memories' [patent_app_type] => 1 [patent_app_number] => 7/754338 [patent_app_country] => US [patent_app_date] => 1991-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9567 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 515 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371855.pdf [firstpage_image] =>[orig_patent_app_number] => 754338 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/754338
Disc cache subsystem having plural-level cache memories Sep 3, 1991 Issued
Array ( [id] => 3108444 [patent_doc_number] => 05291614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Real-time, concurrent, multifunction digital signal processor subsystem for personal computers' [patent_app_type] => 1 [patent_app_number] => 7/753505 [patent_app_country] => US [patent_app_date] => 1991-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8787 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 544 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291614.pdf [firstpage_image] =>[orig_patent_app_number] => 753505 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/753505
Real-time, concurrent, multifunction digital signal processor subsystem for personal computers Sep 2, 1991 Issued
Array ( [id] => 2977787 [patent_doc_number] => 05274834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Transparent system interrupts with integrated extended memory addressing' [patent_app_type] => 1 [patent_app_number] => 7/753605 [patent_app_country] => US [patent_app_date] => 1991-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2915 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274834.pdf [firstpage_image] =>[orig_patent_app_number] => 753605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/753605
Transparent system interrupts with integrated extended memory addressing Aug 29, 1991 Issued
07/753107 TRANSPARENT SYSTEM INTERRUPTS WITH AUTOMATED INPUT/OUTPUT TRAP RESTART Aug 29, 1991 Abandoned
Array ( [id] => 2913969 [patent_doc_number] => 05218691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Disk emulation system' [patent_app_type] => 1 [patent_app_number] => 7/753269 [patent_app_country] => US [patent_app_date] => 1991-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 80 [patent_no_of_words] => 42723 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/218/05218691.pdf [firstpage_image] =>[orig_patent_app_number] => 753269 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/753269
Disk emulation system Aug 29, 1991 Issued
Array ( [id] => 3494852 [patent_doc_number] => 05446844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Peripheral memory interface controller as a cache for a large data processing system' [patent_app_type] => 1 [patent_app_number] => 7/741963 [patent_app_country] => US [patent_app_date] => 1991-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4016 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446844.pdf [firstpage_image] =>[orig_patent_app_number] => 741963 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/741963
Peripheral memory interface controller as a cache for a large data processing system Aug 4, 1991 Issued
Array ( [id] => 2930589 [patent_doc_number] => 05193194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Concurrent arbitration system and method for bus control' [patent_app_type] => 1 [patent_app_number] => 7/742154 [patent_app_country] => US [patent_app_date] => 1991-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193194.pdf [firstpage_image] =>[orig_patent_app_number] => 742154 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/742154
Concurrent arbitration system and method for bus control Jul 31, 1991 Issued
Array ( [id] => 2990440 [patent_doc_number] => 05257390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Extended range computer communications link' [patent_app_type] => 1 [patent_app_number] => 7/736508 [patent_app_country] => US [patent_app_date] => 1991-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 8699 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257390.pdf [firstpage_image] =>[orig_patent_app_number] => 736508 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/736508
Extended range computer communications link Jul 25, 1991 Issued
07/734209 MICROPROCESSOR WITH MULTIPLE BUS CONFIGURATIONS Jul 21, 1991 Abandoned
Array ( [id] => 2908631 [patent_doc_number] => 05241683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Data flow type information processor' [patent_app_type] => 1 [patent_app_number] => 7/726402 [patent_app_country] => US [patent_app_date] => 1991-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 8936 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241683.pdf [firstpage_image] =>[orig_patent_app_number] => 726402 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/726402
Data flow type information processor Jul 4, 1991 Issued
Array ( [id] => 2980128 [patent_doc_number] => 05202972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Store buffer apparatus in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 7/725919 [patent_app_country] => US [patent_app_date] => 1991-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10777 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202972.pdf [firstpage_image] =>[orig_patent_app_number] => 725919 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/725919
Store buffer apparatus in a multiprocessor system Jul 2, 1991 Issued
Array ( [id] => 3108426 [patent_doc_number] => 05291613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Method for executing a control instruction in a multi-computer system' [patent_app_type] => 1 [patent_app_number] => 7/724802 [patent_app_country] => US [patent_app_date] => 1991-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5737 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291613.pdf [firstpage_image] =>[orig_patent_app_number] => 724802 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/724802
Method for executing a control instruction in a multi-computer system Jul 1, 1991 Issued
Array ( [id] => 2877035 [patent_doc_number] => 05097409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Multi-processor system with cache memories' [patent_app_type] => 1 [patent_app_number] => 7/719064 [patent_app_country] => US [patent_app_date] => 1991-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7187 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097409.pdf [firstpage_image] =>[orig_patent_app_number] => 719064 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/719064
Multi-processor system with cache memories Jun 17, 1991 Issued
Array ( [id] => 3049945 [patent_doc_number] => 05301296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Microprocessor with cache memory' [patent_app_type] => 1 [patent_app_number] => 7/716411 [patent_app_country] => US [patent_app_date] => 1991-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7361 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301296.pdf [firstpage_image] =>[orig_patent_app_number] => 716411 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/716411
Microprocessor with cache memory Jun 16, 1991 Issued
Array ( [id] => 3458123 [patent_doc_number] => 05420989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Coprocessor interface supporting I/O or memory mapped communications' [patent_app_type] => 1 [patent_app_number] => 7/713812 [patent_app_country] => US [patent_app_date] => 1991-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6477 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420989.pdf [firstpage_image] =>[orig_patent_app_number] => 713812 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/713812
Coprocessor interface supporting I/O or memory mapped communications Jun 11, 1991 Issued
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