Raj R. Gupta

Array ( [id] => 2654781 [patent_doc_number] => 04980820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Interrupt driven prioritized queue' [patent_app_type] => 1 [patent_app_number] => 7/433924 [patent_app_country] => US [patent_app_date] => 1989-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 7772 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980820.pdf [firstpage_image] =>[orig_patent_app_number] => 433924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2651353 [patent_doc_number] => 04939642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-03 [patent_title] => 'Virtual bit map processor' [patent_app_type] => 1 [patent_app_number] => 7/426539 [patent_app_country] => US [patent_app_date] => 1989-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6351 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/939/04939642.pdf [firstpage_image] =>[orig_patent_app_number] => 426539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2672478 [patent_doc_number] => 04947369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-07 [patent_title] => 'Microword generation mechanism utilizing a separate branch decision programmable logic array' [patent_app_type] => 1 [patent_app_number] => 7/416881 [patent_app_country] => US [patent_app_date] => 1989-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12508 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/947/04947369.pdf [firstpage_image] =>[orig_patent_app_number] => 416881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2945188 [patent_doc_number] => 05233693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'First-in first-out storage facility having bypassing loop thereof' [patent_app_type] => 1 [patent_app_number] => 7/399249 [patent_app_country] => US [patent_app_date] => 1989-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4050 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233693.pdf [firstpage_image] =>[orig_patent_app_number] => 399249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3503287 [patent_doc_number] => 05440749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'High performance, low cost microprocessor architecture' [patent_app_type] => 1 [patent_app_number] => 7/389334 [patent_app_country] => US [patent_app_date] => 1989-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 17384 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440749.pdf [firstpage_image] =>[orig_patent_app_number] => 389334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2725857 [patent_doc_number] => 05008819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-16 [patent_title] => 'Memory spaced array' [patent_app_type] => 1 [patent_app_number] => 7/383235 [patent_app_country] => US [patent_app_date] => 1989-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13684 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/008/05008819.pdf [firstpage_image] =>[orig_patent_app_number] => 383235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2757519 [patent_doc_number] => 05031092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Microcomputer with high density ram in separate isolation well on single chip' [patent_app_type] => 1 [patent_app_number] => 7/380198 [patent_app_country] => US [patent_app_date] => 1989-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 20958 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031092.pdf [firstpage_image] =>[orig_patent_app_number] => 380198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2866281 [patent_doc_number] => 05127099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Method and apparatus for securing access to a ladder logic programming and monitoring system' [patent_app_type] => 1 [patent_app_number] => 7/375270 [patent_app_country] => US [patent_app_date] => 1989-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 3418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/127/05127099.pdf [firstpage_image] =>[orig_patent_app_number] => 375270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2714888 [patent_doc_number] => 05068781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-26 [patent_title] => 'Method and apparatus for managing multiple lock indicators in a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 7/372565 [patent_app_country] => US [patent_app_date] => 1989-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10412 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 464 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/068/05068781.pdf [firstpage_image] =>[orig_patent_app_number] => 372565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2839731 [patent_doc_number] => 05099414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-24 [patent_title] => 'Interrupt handling in a multi-processor data processing system' [patent_app_type] => 1 [patent_app_number] => 7/364881 [patent_app_country] => US [patent_app_date] => 1989-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2711 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/099/05099414.pdf [firstpage_image] =>[orig_patent_app_number] => 364881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2753353 [patent_doc_number] => 04987532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-22 [patent_title] => 'Electronic computer system with means for issuing a non-store request before executing state transition prosecution' [patent_app_type] => 1 [patent_app_number] => 7/358805 [patent_app_country] => US [patent_app_date] => 1989-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3229 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/987/04987532.pdf [firstpage_image] =>[orig_patent_app_number] => 358805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2892163 [patent_doc_number] => 05119499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Host processor which includes apparatus for performing coprocessor functions' [patent_app_type] => 1 [patent_app_number] => 7/356422 [patent_app_country] => US [patent_app_date] => 1989-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3267 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/119/05119499.pdf [firstpage_image] =>[orig_patent_app_number] => 356422 [rel_patent_id] =>[rel_patent_doc_number] =>)