Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2861743 [patent_doc_number] => 05089990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-18 [patent_title] => 'Word processor with column layout function' [patent_app_type] => 1 [patent_app_number] => 7/296363 [patent_app_country] => US [patent_app_date] => 1989-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 37 [patent_no_of_words] => 5533 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/089/05089990.pdf [firstpage_image] =>[orig_patent_app_number] => 296363 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/296363
Word processor with column layout function Jan 8, 1989 Issued
07/292189 TWO STAGE CACHE MEMORY SYSTEM AND METHOD Dec 29, 1988 Abandoned
07/291805 STORE BUFFER APPARATUS IN A MULTIPROCESSOR COMPUTER SYSTEM Dec 28, 1988 Abandoned
07/291888 CACHE BYPASS APPARATUS Dec 28, 1988 Abandoned
Array ( [id] => 2715045 [patent_doc_number] => 04992932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Data processing device with data buffer control' [patent_app_type] => 1 [patent_app_number] => 7/290335 [patent_app_country] => US [patent_app_date] => 1988-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7704 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992932.pdf [firstpage_image] =>[orig_patent_app_number] => 290335 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/290335
Data processing device with data buffer control Dec 26, 1988 Issued
07/289202 PIPELINE PROCESSOR WITH PREFETCH CIRCUIT Dec 22, 1988 Abandoned
Array ( [id] => 2771170 [patent_doc_number] => RE034052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage' [patent_app_type] => 2 [patent_app_number] => 7/285827 [patent_app_country] => US [patent_app_date] => 1988-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5015 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 30 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/034/RE034052.pdf [firstpage_image] =>[orig_patent_app_number] => 285827 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/285827
Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage Dec 15, 1988 Issued
Array ( [id] => 2691987 [patent_doc_number] => 05046041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'Device for transmitting information between a plurality of elements of an automobile vehicle, and a central information processing unit' [patent_app_type] => 1 [patent_app_number] => 7/284604 [patent_app_country] => US [patent_app_date] => 1988-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1322 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/046/05046041.pdf [firstpage_image] =>[orig_patent_app_number] => 284604 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/284604
Device for transmitting information between a plurality of elements of an automobile vehicle, and a central information processing unit Dec 14, 1988 Issued
07/282540 REFRESH CONTROL FOR DYNAMIC MEMORY IN MULTIPLE PROCESSOR SYSTEM Dec 8, 1988 Abandoned
Array ( [id] => 2667165 [patent_doc_number] => 04979102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-18 [patent_title] => 'Microprocessor operable under direct connection to coprocessor' [patent_app_type] => 1 [patent_app_number] => 7/279795 [patent_app_country] => US [patent_app_date] => 1988-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2458 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/979/04979102.pdf [firstpage_image] =>[orig_patent_app_number] => 279795 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/279795
Microprocessor operable under direct connection to coprocessor Dec 4, 1988 Issued
Array ( [id] => 2588344 [patent_doc_number] => 04974145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-27 [patent_title] => 'Processor system including a paging processor for controlling paging between a main storage and an extended storage' [patent_app_type] => 1 [patent_app_number] => 7/277949 [patent_app_country] => US [patent_app_date] => 1988-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9555 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/974/04974145.pdf [firstpage_image] =>[orig_patent_app_number] => 277949 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/277949
Processor system including a paging processor for controlling paging between a main storage and an extended storage Nov 29, 1988 Issued
Array ( [id] => 2702641 [patent_doc_number] => 04996639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Data processor including an A/D converter for converting a plurality of analog input channels into digital data' [patent_app_type] => 1 [patent_app_number] => 7/276970 [patent_app_country] => US [patent_app_date] => 1988-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4765 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996639.pdf [firstpage_image] =>[orig_patent_app_number] => 276970 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/276970
Data processor including an A/D converter for converting a plurality of analog input channels into digital data Nov 27, 1988 Issued
Array ( [id] => 2636382 [patent_doc_number] => 04951250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'Combined input/output circuit for a programmable controller' [patent_app_type] => 1 [patent_app_number] => 7/272973 [patent_app_country] => US [patent_app_date] => 1988-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4766 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/951/04951250.pdf [firstpage_image] =>[orig_patent_app_number] => 272973 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/272973
Combined input/output circuit for a programmable controller Nov 17, 1988 Issued
Array ( [id] => 2617876 [patent_doc_number] => 04903195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-20 [patent_title] => 'Method for controlling data transfer' [patent_app_type] => 1 [patent_app_number] => 7/271381 [patent_app_country] => US [patent_app_date] => 1988-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1855 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/903/04903195.pdf [firstpage_image] =>[orig_patent_app_number] => 271381 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/271381
Method for controlling data transfer Nov 13, 1988 Issued
Array ( [id] => 2730541 [patent_doc_number] => 05025365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-18 [patent_title] => 'Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors' [patent_app_type] => 1 [patent_app_number] => 7/270324 [patent_app_country] => US [patent_app_date] => 1988-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 8068 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/025/05025365.pdf [firstpage_image] =>[orig_patent_app_number] => 270324 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/270324
Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors Nov 13, 1988 Issued
Array ( [id] => 2715116 [patent_doc_number] => 04992936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Address translation method and apparatus therefor' [patent_app_type] => 1 [patent_app_number] => 7/269058 [patent_app_country] => US [patent_app_date] => 1988-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9488 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992936.pdf [firstpage_image] =>[orig_patent_app_number] => 269058 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/269058
Address translation method and apparatus therefor Nov 8, 1988 Issued
07/269171 PROCESSING SYSTEM FOR BRANCH INSTRUCTION Nov 8, 1988 Abandoned
Array ( [id] => 2826370 [patent_doc_number] => 05081572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-14 [patent_title] => 'Manipulation of time-ordered lists and instructions therefor' [patent_app_type] => 1 [patent_app_number] => 7/264289 [patent_app_country] => US [patent_app_date] => 1988-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6551 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/081/05081572.pdf [firstpage_image] =>[orig_patent_app_number] => 264289 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/264289
Manipulation of time-ordered lists and instructions therefor Oct 27, 1988 Issued
Array ( [id] => 2772378 [patent_doc_number] => 04994962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-19 [patent_title] => 'Variable length cache fill' [patent_app_type] => 1 [patent_app_number] => 7/264260 [patent_app_country] => US [patent_app_date] => 1988-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1434 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/994/04994962.pdf [firstpage_image] =>[orig_patent_app_number] => 264260 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/264260
Variable length cache fill Oct 27, 1988 Issued
Array ( [id] => 2667111 [patent_doc_number] => 04979099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-18 [patent_title] => 'Quasi-fair arbitration scheme with default owner speedup' [patent_app_type] => 1 [patent_app_number] => 7/262574 [patent_app_country] => US [patent_app_date] => 1988-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4780 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/979/04979099.pdf [firstpage_image] =>[orig_patent_app_number] => 262574 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/262574
Quasi-fair arbitration scheme with default owner speedup Oct 24, 1988 Issued
Menu