Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2606040 [patent_doc_number] => 04924379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-08 [patent_title] => 'Multiprocessor system with several processors equipped with cache memories and with a common memory' [patent_app_type] => 1 [patent_app_number] => 7/103491 [patent_app_country] => US [patent_app_date] => 1987-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4031 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/924/04924379.pdf [firstpage_image] =>[orig_patent_app_number] => 103491 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/103491
Multiprocessor system with several processors equipped with cache memories and with a common memory Sep 30, 1987 Issued
Array ( [id] => 2551378 [patent_doc_number] => 04827399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-02 [patent_title] => 'Common file system for a plurality of data processors' [patent_app_type] => 1 [patent_app_number] => 7/102618 [patent_app_country] => US [patent_app_date] => 1987-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2076 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/827/04827399.pdf [firstpage_image] =>[orig_patent_app_number] => 102618 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/102618
Common file system for a plurality of data processors Sep 29, 1987 Issued
Array ( [id] => 2454831 [patent_doc_number] => 04791550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-13 [patent_title] => 'Higher order language-directed computer' [patent_app_type] => 1 [patent_app_number] => 7/103123 [patent_app_country] => US [patent_app_date] => 1987-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/791/04791550.pdf [firstpage_image] =>[orig_patent_app_number] => 103123 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/103123
Higher order language-directed computer Sep 29, 1987 Issued
Array ( [id] => 2500981 [patent_doc_number] => 04843544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-27 [patent_title] => 'Method and apparatus for controlling data transfers through multiple buffers' [patent_app_type] => 1 [patent_app_number] => 7/101354 [patent_app_country] => US [patent_app_date] => 1987-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6216 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/843/04843544.pdf [firstpage_image] =>[orig_patent_app_number] => 101354 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/101354
Method and apparatus for controlling data transfers through multiple buffers Sep 24, 1987 Issued
07/097315 SECONDARY STORAGE FACILITY EMPLOYING SERIAL COMMUNICATION BETWEEN DRIVE & CONTROLLER Sep 13, 1987 Abandoned
Array ( [id] => 2390396 [patent_doc_number] => 04789924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-06 [patent_title] => 'Microprocessor emulation apparatus for debugging a microprocessor of an electronic system without utilizing an interrupt signal and a stop signal to temporarily stop an operation of the system' [patent_app_type] => 1 [patent_app_number] => 7/096201 [patent_app_country] => US [patent_app_date] => 1987-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 36 [patent_no_of_words] => 13269 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 455 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/789/04789924.pdf [firstpage_image] =>[orig_patent_app_number] => 096201 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/096201
Microprocessor emulation apparatus for debugging a microprocessor of an electronic system without utilizing an interrupt signal and a stop signal to temporarily stop an operation of the system Sep 7, 1987 Issued
Array ( [id] => 2451854 [patent_doc_number] => 04757447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-07-12 [patent_title] => 'Virtual memory system having identity marking for common address space' [patent_app_type] => 1 [patent_app_number] => 7/093135 [patent_app_country] => US [patent_app_date] => 1987-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5100 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/757/04757447.pdf [firstpage_image] =>[orig_patent_app_number] => 093135 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/093135
Virtual memory system having identity marking for common address space Sep 2, 1987 Issued
07/092244 INTERRUPTIBLE STRUCTURED MICROPROGRAMMED SIXTEEN-BIT ADDRESS SEQUENCE CONTROLLER Sep 1, 1987 Abandoned
Array ( [id] => 2561336 [patent_doc_number] => 04809029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-28 [patent_title] => 'Gate array large scale integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/088983 [patent_app_country] => US [patent_app_date] => 1987-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5363 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/809/04809029.pdf [firstpage_image] =>[orig_patent_app_number] => 088983 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/088983
Gate array large scale integrated circuit device Aug 20, 1987 Issued
Array ( [id] => 2498860 [patent_doc_number] => 04829466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-09 [patent_title] => 'Paging device with modifiable operational characteristics' [patent_app_type] => 1 [patent_app_number] => 7/083874 [patent_app_country] => US [patent_app_date] => 1987-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 30080 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/829/04829466.pdf [firstpage_image] =>[orig_patent_app_number] => 083874 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/083874
Paging device with modifiable operational characteristics Aug 6, 1987 Issued
Array ( [id] => 2628044 [patent_doc_number] => 04894772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-16 [patent_title] => 'Method and apparatus for qualifying branch cache entries' [patent_app_type] => 1 [patent_app_number] => 7/080452 [patent_app_country] => US [patent_app_date] => 1987-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6833 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/894/04894772.pdf [firstpage_image] =>[orig_patent_app_number] => 080452 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/080452
Method and apparatus for qualifying branch cache entries Jul 30, 1987 Issued
Array ( [id] => 2646354 [patent_doc_number] => 04914577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-03 [patent_title] => 'Dynamic memory management system and method' [patent_app_type] => 1 [patent_app_number] => 7/074310 [patent_app_country] => US [patent_app_date] => 1987-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 19921 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/914/04914577.pdf [firstpage_image] =>[orig_patent_app_number] => 074310 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/074310
Dynamic memory management system and method Jul 15, 1987 Issued
Array ( [id] => 2560664 [patent_doc_number] => 04807111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-21 [patent_title] => 'Dynamic queueing method' [patent_app_type] => 1 [patent_app_number] => 7/064911 [patent_app_country] => US [patent_app_date] => 1987-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18208 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/807/04807111.pdf [firstpage_image] =>[orig_patent_app_number] => 064911 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/064911
Dynamic queueing method Jun 18, 1987 Issued
07/061602 APPARATUS AND METHOD FOR FORMING A SEQUENCER LINK FOR A SEQUENCER CONTROLLED BY A MICROPROGRAM Jun 18, 1987 Abandoned
Array ( [id] => 2530317 [patent_doc_number] => 04881164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-14 [patent_title] => 'Multi-microprocessor for controlling shared memory' [patent_app_type] => 1 [patent_app_number] => 7/051178 [patent_app_country] => US [patent_app_date] => 1987-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5602 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/881/04881164.pdf [firstpage_image] =>[orig_patent_app_number] => 051178 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/051178
Multi-microprocessor for controlling shared memory May 17, 1987 Issued
Array ( [id] => 2573048 [patent_doc_number] => 04858116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-15 [patent_title] => 'Method and apparatus for managing multiple lock indicators in a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 7/044954 [patent_app_country] => US [patent_app_date] => 1987-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10419 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/858/04858116.pdf [firstpage_image] =>[orig_patent_app_number] => 044954 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/044954
Method and apparatus for managing multiple lock indicators in a multiprocessor computer system Apr 30, 1987 Issued
Array ( [id] => 2523921 [patent_doc_number] => 04852022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'Instructions seqencer for microprocessor with matrix for determining the instructions cycle steps' [patent_app_type] => 1 [patent_app_number] => 7/057058 [patent_app_country] => US [patent_app_date] => 1987-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2279 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/852/04852022.pdf [firstpage_image] =>[orig_patent_app_number] => 057058 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/057058
Instructions seqencer for microprocessor with matrix for determining the instructions cycle steps Apr 29, 1987 Issued
Array ( [id] => 2430195 [patent_doc_number] => 04780809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-25 [patent_title] => 'Apparatus for storing data with deferred uncorrectable error reporting' [patent_app_type] => 1 [patent_app_number] => 7/045756 [patent_app_country] => US [patent_app_date] => 1987-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5516 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/780/04780809.pdf [firstpage_image] =>[orig_patent_app_number] => 045756 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/045756
Apparatus for storing data with deferred uncorrectable error reporting Apr 27, 1987 Issued
Array ( [id] => 2523975 [patent_doc_number] => 04819166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-04 [patent_title] => 'Multimode scan apparatus' [patent_app_type] => 1 [patent_app_number] => 7/040738 [patent_app_country] => US [patent_app_date] => 1987-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5334 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/819/04819166.pdf [firstpage_image] =>[orig_patent_app_number] => 040738 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/040738
Multimode scan apparatus Apr 14, 1987 Issued
Array ( [id] => 2569144 [patent_doc_number] => 04837678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-06 [patent_title] => 'Instruction sequencer for parallel operation of functional units' [patent_app_type] => 1 [patent_app_number] => 7/035349 [patent_app_country] => US [patent_app_date] => 1987-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 9551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/837/04837678.pdf [firstpage_image] =>[orig_patent_app_number] => 035349 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/035349
Instruction sequencer for parallel operation of functional units Apr 6, 1987 Issued
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