| Application number | Title of the application | Filing Date | Status |
|---|
| 90/000499 | CENTRAL OFFICE MASSIVE MEMORY RECORDING SYSTEM | Feb 9, 1984 | Issued |
Array
(
[id] => 2223328
[patent_doc_number] => 04621342
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-11-04
[patent_title] => 'Arbitration circuitry for deciding access requests from a multiplicity of components'
[patent_app_type] => 1
[patent_app_number] => 6/575837
[patent_app_country] => US
[patent_app_date] => 1984-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4376
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 490
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/621/04621342.pdf
[firstpage_image] =>[orig_patent_app_number] => 575837
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/575837 | Arbitration circuitry for deciding access requests from a multiplicity of components | Jan 31, 1984 | Issued |
Array
(
[id] => 2159875
[patent_doc_number] => 04518961
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-05-21
[patent_title] => 'Universal paging device with power conservation'
[patent_app_type] => 1
[patent_app_number] => 6/575472
[patent_app_country] => US
[patent_app_date] => 1984-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 47
[patent_no_of_words] => 29537
[patent_no_of_claims] => 103
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/518/04518961.pdf
[firstpage_image] =>[orig_patent_app_number] => 575472
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/575472 | Universal paging device with power conservation | Jan 29, 1984 | Issued |
Array
(
[id] => 2176668
[patent_doc_number] => 04538226
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-08-27
[patent_title] => 'Buffer control system'
[patent_app_type] => 1
[patent_app_number] => 6/573745
[patent_app_country] => US
[patent_app_date] => 1984-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3661
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/538/04538226.pdf
[firstpage_image] =>[orig_patent_app_number] => 573745
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/573745 | Buffer control system | Jan 24, 1984 | Issued |
Array
(
[id] => 2335204
[patent_doc_number] => 04672573
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-06-09
[patent_title] => 'Programmable controller with improved return processing capabilities after a power interruption'
[patent_app_type] => 1
[patent_app_number] => 6/571750
[patent_app_country] => US
[patent_app_date] => 1984-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1549
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/672/04672573.pdf
[firstpage_image] =>[orig_patent_app_number] => 571750
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/571750 | Programmable controller with improved return processing capabilities after a power interruption | Jan 17, 1984 | Issued |
| 06/570412 | SECONDARY STORAGE FACILITY EMPLOYING SERIAL COMMUNICATIONS BETWEEN DRIVE AND CONTROLLER | Jan 11, 1984 | Abandoned |
Array
(
[id] => 2568043
[patent_doc_number] => 04853891
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-01
[patent_title] => 'Memory-programmable controller'
[patent_app_type] => 1
[patent_app_number] => 6/568115
[patent_app_country] => US
[patent_app_date] => 1984-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2570
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/853/04853891.pdf
[firstpage_image] =>[orig_patent_app_number] => 568115
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/568115 | Memory-programmable controller | Jan 3, 1984 | Issued |
Array
(
[id] => 2317425
[patent_doc_number] => 04646232
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-02-24
[patent_title] => 'Microprocessor with integrated CPU, RAM, timer, bus arbiter data for communication system'
[patent_app_type] => 1
[patent_app_number] => 6/567596
[patent_app_country] => US
[patent_app_date] => 1984-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 25
[patent_no_of_words] => 22317
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/646/04646232.pdf
[firstpage_image] =>[orig_patent_app_number] => 567596
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/567596 | Microprocessor with integrated CPU, RAM, timer, bus arbiter data for communication system | Jan 2, 1984 | Issued |
| 06/567304 | MULTI-MICROPROCESSOR FOR CONTROLLING SHARED MEMORY | Dec 29, 1983 | Abandoned |
Array
(
[id] => 2287025
[patent_doc_number] => 04627020
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-12-02
[patent_title] => 'Method for rotating a binary image'
[patent_app_type] => 1
[patent_app_number] => 6/567214
[patent_app_country] => US
[patent_app_date] => 1983-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3720
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/627/04627020.pdf
[firstpage_image] =>[orig_patent_app_number] => 567214
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/567214 | Method for rotating a binary image | Dec 29, 1983 | Issued |
Array
(
[id] => 2265731
[patent_doc_number] => 04598356
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-07-01
[patent_title] => 'Data processing system including a main processor and a co-processor and co-processor error handling logic'
[patent_app_type] => 1
[patent_app_number] => 6/567296
[patent_app_country] => US
[patent_app_date] => 1983-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3391
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/598/04598356.pdf
[firstpage_image] =>[orig_patent_app_number] => 567296
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/567296 | Data processing system including a main processor and a co-processor and co-processor error handling logic | Dec 29, 1983 | Issued |
| 06/565565 | DATA PROCESSOR UNIT COMPRISING A CONTROL SECTION WHICH COMPRISES AN ADDRESS GENERATOR FOR GENERATING ADDRESSES WHICH ARE COMPOSED OF CHARACTERISTIC ADDRESS PORTIONS | Dec 26, 1983 | Abandoned |
Array
(
[id] => 2336148
[patent_doc_number] => 04635187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-01-06
[patent_title] => 'Control for a multiprocessing system program process'
[patent_app_type] => 1
[patent_app_number] => 6/563255
[patent_app_country] => US
[patent_app_date] => 1983-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5248
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/635/04635187.pdf
[firstpage_image] =>[orig_patent_app_number] => 563255
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/563255 | Control for a multiprocessing system program process | Dec 18, 1983 | Issued |
| 06/558024 | VIRTUAL BIT MAP PROCESSOR | Dec 4, 1983 | Abandoned |
Array
(
[id] => 2183340
[patent_doc_number] => 04558412
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1985-12-10
[patent_title] => 'Direct memory access revolving priority apparatus'
[patent_app_type] => 1
[patent_app_number] => 6/557379
[patent_app_country] => US
[patent_app_date] => 1983-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3387
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 432
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/558/04558412.pdf
[firstpage_image] =>[orig_patent_app_number] => 557379
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/557379 | Direct memory access revolving priority apparatus | Nov 30, 1983 | Issued |
| 06/555857 | VIRTUAL MEMORY SYSTEM HAVING IDENTITY MARKING FOR COMMON ADDRESS SPACE | Nov 27, 1983 | Abandoned |
| 06/555028 | HIGH SPEED LOCAL BUS AND DATA TRANSFER METHOD | Nov 24, 1983 | Abandoned |
Array
(
[id] => 2822720
[patent_doc_number] => 05079694
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Data processing apparatus having a working memory area'
[patent_app_type] => 1
[patent_app_number] => 6/554407
[patent_app_country] => US
[patent_app_date] => 1983-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3228
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/079/05079694.pdf
[firstpage_image] =>[orig_patent_app_number] => 554407
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/554407 | Data processing apparatus having a working memory area | Nov 21, 1983 | Issued |
Array
(
[id] => 2363907
[patent_doc_number] => 04658356
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-04-14
[patent_title] => 'Control system for updating a change bit'
[patent_app_type] => 1
[patent_app_number] => 6/553235
[patent_app_country] => US
[patent_app_date] => 1983-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3129
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/658/04658356.pdf
[firstpage_image] =>[orig_patent_app_number] => 553235
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/553235 | Control system for updating a change bit | Nov 17, 1983 | Issued |
| 06/552602 | MICROCOMPUTER | Nov 15, 1983 | Abandoned |