Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
06/486531 GATE ARRAY LARGE SCALE INTEGRATED CIRCUIT DEVICE Apr 18, 1983 Abandoned
06/485811 METHOD AND APPARATUS FOR INTERRUPTING A COPROCESSOR Apr 17, 1983 Abandoned
Array ( [id] => 2251951 [patent_doc_number] => 04633431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-30 [patent_title] => 'Arrangement for coupling digital processing units' [patent_app_type] => 1 [patent_app_number] => 6/486060 [patent_app_country] => US [patent_app_date] => 1983-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5326 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/633/04633431.pdf [firstpage_image] =>[orig_patent_app_number] => 486060 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/486060
Arrangement for coupling digital processing units Apr 17, 1983 Issued
Array ( [id] => 2249452 [patent_doc_number] => 04569015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-02-04 [patent_title] => 'Method for achieving multiple processor agreement optimized for no faults' [patent_app_type] => 1 [patent_app_number] => 6/485573 [patent_app_country] => US [patent_app_date] => 1983-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5600 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/569/04569015.pdf [firstpage_image] =>[orig_patent_app_number] => 485573 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/485573
Method for achieving multiple processor agreement optimized for no faults Apr 12, 1983 Issued
Array ( [id] => 2309079 [patent_doc_number] => 04642757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-02-10 [patent_title] => 'Microinstruction controlled arithmetic control unit' [patent_app_type] => 1 [patent_app_number] => 6/484260 [patent_app_country] => US [patent_app_date] => 1983-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 5294 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/642/04642757.pdf [firstpage_image] =>[orig_patent_app_number] => 484260 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/484260
Microinstruction controlled arithmetic control unit Apr 11, 1983 Issued
Array ( [id] => 2309057 [patent_doc_number] => 04642755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-02-10 [patent_title] => 'Shared memory with two distinct addressing structures' [patent_app_type] => 1 [patent_app_number] => 6/481056 [patent_app_country] => US [patent_app_date] => 1983-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 39 [patent_no_of_words] => 18996 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/642/04642755.pdf [firstpage_image] =>[orig_patent_app_number] => 481056 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/481056
Shared memory with two distinct addressing structures Mar 30, 1983 Issued
Array ( [id] => 2147216 [patent_doc_number] => 04553201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-11-12 [patent_title] => 'Decoupling apparatus for verification of a processor independent from an associated data processing system' [patent_app_type] => 1 [patent_app_number] => 6/479790 [patent_app_country] => US [patent_app_date] => 1983-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2243 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/553/04553201.pdf [firstpage_image] =>[orig_patent_app_number] => 479790 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/479790
Decoupling apparatus for verification of a processor independent from an associated data processing system Mar 27, 1983 Issued
Array ( [id] => 2204198 [patent_doc_number] => 04527235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-07-02 [patent_title] => 'Subscriber terminal polling unit' [patent_app_type] => 1 [patent_app_number] => 6/475470 [patent_app_country] => US [patent_app_date] => 1983-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3731 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/527/04527235.pdf [firstpage_image] =>[orig_patent_app_number] => 475470 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/475470
Subscriber terminal polling unit Mar 14, 1983 Issued
Array ( [id] => 2163995 [patent_doc_number] => 04554627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-11-19 [patent_title] => 'Data processing system having a unique micro-sequencing system' [patent_app_type] => 1 [patent_app_number] => 6/473560 [patent_app_country] => US [patent_app_date] => 1983-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1239 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/554/04554627.pdf [firstpage_image] =>[orig_patent_app_number] => 473560 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/473560
Data processing system having a unique micro-sequencing system Mar 8, 1983 Issued
Array ( [id] => 2072286 [patent_doc_number] => 04430702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-02-07 [patent_title] => 'Network access device' [patent_app_type] => 1 [patent_app_number] => 6/471568 [patent_app_country] => US [patent_app_date] => 1983-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 36 [patent_no_of_words] => 19752 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/430/04430702.pdf [firstpage_image] =>[orig_patent_app_number] => 471568 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/471568
Network access device Mar 1, 1983 Issued
Array ( [id] => 2125103 [patent_doc_number] => 04481581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-06 [patent_title] => 'Sequence control circuit for a computer' [patent_app_type] => 1 [patent_app_number] => 6/470249 [patent_app_country] => US [patent_app_date] => 1983-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5333 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/481/04481581.pdf [firstpage_image] =>[orig_patent_app_number] => 470249 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/470249
Sequence control circuit for a computer Feb 27, 1983 Issued
Array ( [id] => 2250239 [patent_doc_number] => 04613936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-09-23 [patent_title] => 'Centralized generation of data transfer acknowledge pulses for microprocessors' [patent_app_type] => 1 [patent_app_number] => 6/470025 [patent_app_country] => US [patent_app_date] => 1983-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1896 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/613/04613936.pdf [firstpage_image] =>[orig_patent_app_number] => 470025 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/470025
Centralized generation of data transfer acknowledge pulses for microprocessors Feb 24, 1983 Issued
Array ( [id] => 2188010 [patent_doc_number] => 04504907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-12 [patent_title] => 'High speed data base search system' [patent_app_type] => 1 [patent_app_number] => 6/469610 [patent_app_country] => US [patent_app_date] => 1983-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 89 [patent_figures_cnt] => 110 [patent_no_of_words] => 18367 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/504/04504907.pdf [firstpage_image] =>[orig_patent_app_number] => 469610 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/469610
High speed data base search system Feb 23, 1983 Issued
06/466389 DEVICE INTERFACE CONTROLLER FOR INPUT/OUTPUT COMMUNICATION Feb 13, 1983 Abandoned
06/466327 SIZE CONFIGURABLE DATA STORAGE SYSTEM Feb 13, 1983 Abandoned
Array ( [id] => 2125089 [patent_doc_number] => 04481580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-06 [patent_title] => 'Distributed data transfer control for parallel processor architectures' [patent_app_type] => 1 [patent_app_number] => 6/461334 [patent_app_country] => US [patent_app_date] => 1983-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 59 [patent_no_of_words] => 18062 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 779 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/481/04481580.pdf [firstpage_image] =>[orig_patent_app_number] => 461334 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/461334
Distributed data transfer control for parallel processor architectures Jan 26, 1983 Issued
Array ( [id] => 2389632 [patent_doc_number] => 04783739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-08 [patent_title] => 'Input/output command processor' [patent_app_type] => 1 [patent_app_number] => 6/459333 [patent_app_country] => US [patent_app_date] => 1983-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 125 [patent_figures_cnt] => 147 [patent_no_of_words] => 42049 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/783/04783739.pdf [firstpage_image] =>[orig_patent_app_number] => 459333 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/459333
Input/output command processor Jan 18, 1983 Issued
Array ( [id] => 2283265 [patent_doc_number] => 04607332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-08-19 [patent_title] => 'Dynamic alteration of firmware programs in Read-Only Memory based systems' [patent_app_type] => 1 [patent_app_number] => 6/457974 [patent_app_country] => US [patent_app_date] => 1983-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1672 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/607/04607332.pdf [firstpage_image] =>[orig_patent_app_number] => 457974 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/457974
Dynamic alteration of firmware programs in Read-Only Memory based systems Jan 13, 1983 Issued
06/452554 MICROWORD GENERATION MECHANISM UTILIZING A SEAPRATE BRANCH DECISION PROGRAMMABLE LOGIC ARRAY Dec 11, 1982 Abandoned
Array ( [id] => 2133544 [patent_doc_number] => 04543626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-09-24 [patent_title] => 'Apparatus and method for controlling digital data processing system employing multiple processors' [patent_app_type] => 1 [patent_app_number] => 6/447228 [patent_app_country] => US [patent_app_date] => 1982-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7138 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/543/04543626.pdf [firstpage_image] =>[orig_patent_app_number] => 447228 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/447228
Apparatus and method for controlling digital data processing system employing multiple processors Dec 5, 1982 Issued
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