Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2089378 [patent_doc_number] => 04435757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-06 [patent_title] => 'Clock control for digital computer' [patent_app_type] => 1 [patent_app_number] => 6/279053 [patent_app_country] => US [patent_app_date] => 1981-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5823 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/435/04435757.pdf [firstpage_image] =>[orig_patent_app_number] => 279053 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/279053
Clock control for digital computer Jun 29, 1981 Issued
Array ( [id] => 2011944 [patent_doc_number] => 04399507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-08-16 [patent_title] => 'Instruction address stack in the data memory of an instruction-pipelined processor' [patent_app_type] => 1 [patent_app_number] => 6/280417 [patent_app_country] => US [patent_app_date] => 1981-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9723 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 769 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/399/04399507.pdf [firstpage_image] =>[orig_patent_app_number] => 280417 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/280417
Instruction address stack in the data memory of an instruction-pipelined processor Jun 29, 1981 Issued
Array ( [id] => 2198125 [patent_doc_number] => 04502111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-02-26 [patent_title] => 'Token generator' [patent_app_type] => 1 [patent_app_number] => 6/268370 [patent_app_country] => US [patent_app_date] => 1981-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 5088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/502/04502111.pdf [firstpage_image] =>[orig_patent_app_number] => 268370 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/268370
Token generator May 28, 1981 Issued
06/266534 DIGITAL DATA PROCESSING SYSTEM EMPLOYING AN OBJECT-BASED ADDRESSING SYSTEM WITH A SINGLE OBJECT TABLE May 21, 1981 Abandoned
06/266429 DIGITAL DATA PROCESSING SYSTEM May 21, 1981 Abandoned
06/266530 UNIVERSAL ADDRESSING SYSTEM FOR A DIGITAL DATA PROCESSING SYSTEM May 21, 1981 Abandoned
06/265257 CONTROLLER FOR PERIPHERAL DATA STORAGE UNITS May 18, 1981 Abandoned
Array ( [id] => 2057839 [patent_doc_number] => 04394727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-07-19 [patent_title] => 'Multi-processor task dispatching apparatus' [patent_app_type] => 1 [patent_app_number] => 6/260543 [patent_app_country] => US [patent_app_date] => 1981-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 10960 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/394/04394727.pdf [firstpage_image] =>[orig_patent_app_number] => 260543 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/260543
Multi-processor task dispatching apparatus May 3, 1981 Issued
Array ( [id] => 2142295 [patent_doc_number] => 04494185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-01-15 [patent_title] => 'Data processing system employing broadcast packet switching' [patent_app_type] => 1 [patent_app_number] => 6/254850 [patent_app_country] => US [patent_app_date] => 1981-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 27601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/494/04494185.pdf [firstpage_image] =>[orig_patent_app_number] => 254850 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/254850
Data processing system employing broadcast packet switching Apr 15, 1981 Issued
Array ( [id] => 2025917 [patent_doc_number] => 04395757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-07-26 [patent_title] => 'Process synchronization utilizing semaphores' [patent_app_type] => 1 [patent_app_number] => 6/254184 [patent_app_country] => US [patent_app_date] => 1981-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 33148 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/395/04395757.pdf [firstpage_image] =>[orig_patent_app_number] => 254184 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/254184
Process synchronization utilizing semaphores Apr 13, 1981 Issued
06/243255 METHOD AND APPARATUS FOR TRACING A SEQUENCE COMPRISING A SERIES OF TRANSFERS OF BINARY MESSAGE WORDS Mar 11, 1981 Abandoned
Array ( [id] => 2041657 [patent_doc_number] => 04414622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-08 [patent_title] => 'Addressing system for a computer, including a mode register' [patent_app_type] => 1 [patent_app_number] => 6/235377 [patent_app_country] => US [patent_app_date] => 1981-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2948 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/414/04414622.pdf [firstpage_image] =>[orig_patent_app_number] => 235377 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/235377
Addressing system for a computer, including a mode register Feb 18, 1981 Issued
Array ( [id] => 2065429 [patent_doc_number] => 04428048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-24 [patent_title] => 'Multiprocessor with staggered processing' [patent_app_type] => 1 [patent_app_number] => 6/229269 [patent_app_country] => US [patent_app_date] => 1981-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4171 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/428/04428048.pdf [firstpage_image] =>[orig_patent_app_number] => 229269 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/229269
Multiprocessor with staggered processing Jan 27, 1981 Issued
Array ( [id] => 2044797 [patent_doc_number] => 04418385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-29 [patent_title] => 'Method and device for arbitration of access conflicts between an asynchronous trap and a program in a critical section' [patent_app_type] => 1 [patent_app_number] => 6/227223 [patent_app_country] => US [patent_app_date] => 1981-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8180 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/418/04418385.pdf [firstpage_image] =>[orig_patent_app_number] => 227223 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/227223
Method and device for arbitration of access conflicts between an asynchronous trap and a program in a critical section Jan 21, 1981 Issued
Array ( [id] => 2000211 [patent_doc_number] => 04384327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-05-17 [patent_title] => 'Intersystem cycle control logic' [patent_app_type] => 1 [patent_app_number] => 6/223540 [patent_app_country] => US [patent_app_date] => 1981-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 42 [patent_no_of_words] => 62854 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/384/04384327.pdf [firstpage_image] =>[orig_patent_app_number] => 223540 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/223540
Intersystem cycle control logic Jan 7, 1981 Issued
Array ( [id] => 2130198 [patent_doc_number] => 04426680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-17 [patent_title] => 'Data processor using read only memories for optimizing main memory access and identifying the starting position of an operand' [patent_app_type] => 1 [patent_app_number] => 6/219809 [patent_app_country] => US [patent_app_date] => 1980-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 11 [patent_no_of_words] => 11322 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/426/04426680.pdf [firstpage_image] =>[orig_patent_app_number] => 219809 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/219809
Data processor using read only memories for optimizing main memory access and identifying the starting position of an operand Dec 23, 1980 Issued
Array ( [id] => 2209517 [patent_doc_number] => 04545011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-10-01 [patent_title] => 'Enhanced communications network testing and control system' [patent_app_type] => 1 [patent_app_number] => 6/215135 [patent_app_country] => US [patent_app_date] => 1980-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 18448 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/545/04545011.pdf [firstpage_image] =>[orig_patent_app_number] => 215135 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/215135
Enhanced communications network testing and control system Dec 9, 1980 Issued
Array ( [id] => 2021250 [patent_doc_number] => 04403285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-09-06 [patent_title] => 'System for automatically releasing a dead lock state in a data processing system' [patent_app_type] => 1 [patent_app_number] => 6/214201 [patent_app_country] => US [patent_app_date] => 1980-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 5580 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/403/04403285.pdf [firstpage_image] =>[orig_patent_app_number] => 214201 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/214201
System for automatically releasing a dead lock state in a data processing system Dec 7, 1980 Issued
06/194000 SYSTEM OF DATA EXCHANGE BETWEEN A NUMBER OF DATA PROCESSORS Oct 5, 1980 Abandoned
Array ( [id] => 2132454 [patent_doc_number] => 04432050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-02-14 [patent_title] => 'Data processing system write protection mechanism' [patent_app_type] => 1 [patent_app_number] => 6/192875 [patent_app_country] => US [patent_app_date] => 1980-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 14045 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/432/04432050.pdf [firstpage_image] =>[orig_patent_app_number] => 192875 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/192875
Data processing system write protection mechanism Sep 30, 1980 Issued
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