Search

Raj R. Gupta

Examiner (ID: 12575, Phone: (571)270-5707 , Office: P/2829 )

Most Active Art Unit
2829
Art Unit(s)
2829, 2893, 2814
Total Applications
829
Issued Applications
593
Pending Applications
52
Abandoned Applications
205

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1949632 [patent_doc_number] => 04342085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-07-27 [patent_title] => 'Stem processing for data reduction in a dictionary storage file' [patent_app_type] => 1 [patent_app_number] => 6/001123 [patent_app_country] => US [patent_app_date] => 1979-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5155 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/342/04342085.pdf [firstpage_image] =>[orig_patent_app_number] => 001123 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/001123
Stem processing for data reduction in a dictionary storage file Jan 4, 1979 Issued
Array ( [id] => 1920008 [patent_doc_number] => 04277827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-07-07 [patent_title] => 'Microprocessor based system for the development and emulation of programmable calculator control read only memory software' [patent_app_type] => 1 [patent_app_number] => 6/000615 [patent_app_country] => US [patent_app_date] => 1979-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10127 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/277/04277827.pdf [firstpage_image] =>[orig_patent_app_number] => 000615 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/000615
Microprocessor based system for the development and emulation of programmable calculator control read only memory software Jan 1, 1979 Issued
Array ( [id] => 1920629 [patent_doc_number] => 04291371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-09-22 [patent_title] => 'I/O Request interrupt mechanism' [patent_app_type] => 1 [patent_app_number] => 6/000315 [patent_app_country] => US [patent_app_date] => 1979-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9488 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/291/04291371.pdf [firstpage_image] =>[orig_patent_app_number] => 000315 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/000315
I/O Request interrupt mechanism Jan 1, 1979 Issued
Array ( [id] => 1914920 [patent_doc_number] => 04271467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-02 [patent_title] => 'I/O Priority resolver' [patent_app_type] => 1 [patent_app_number] => 6/000477 [patent_app_country] => US [patent_app_date] => 1979-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9624 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/271/04271467.pdf [firstpage_image] =>[orig_patent_app_number] => 000477 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/000477
I/O Priority resolver Jan 1, 1979 Issued
Array ( [id] => 1903547 [patent_doc_number] => 04276596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-06-30 [patent_title] => 'Short operand alignment and merge operation' [patent_app_type] => 1 [patent_app_number] => 6/000401 [patent_app_country] => US [patent_app_date] => 1979-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 8 [patent_no_of_words] => 29101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/276/04276596.pdf [firstpage_image] =>[orig_patent_app_number] => 000401 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/000401
Short operand alignment and merge operation Jan 1, 1979 Issued
Array ( [id] => 1900990 [patent_doc_number] => 04293907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-10-06 [patent_title] => 'Data processing apparatus having op-code extension register' [patent_app_type] => 1 [patent_app_number] => 5/974426 [patent_app_country] => US [patent_app_date] => 1978-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9220 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/293/04293907.pdf [firstpage_image] =>[orig_patent_app_number] => 974426 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/974426
Data processing apparatus having op-code extension register Dec 28, 1978 Issued
Array ( [id] => 1965538 [patent_doc_number] => 04315308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-02-09 [patent_title] => 'Interface between a microprocessor chip and peripheral subsystems' [patent_app_type] => 1 [patent_app_number] => 5/972007 [patent_app_country] => US [patent_app_date] => 1978-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5237 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/315/04315308.pdf [firstpage_image] =>[orig_patent_app_number] => 972007 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/972007
Interface between a microprocessor chip and peripheral subsystems Dec 20, 1978 Issued
Array ( [id] => 1951954 [patent_doc_number] => 04313158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-01-26 [patent_title] => 'Cache apparatus for enabling overlap of instruction fetch operations' [patent_app_type] => 1 [patent_app_number] => 5/968049 [patent_app_country] => US [patent_app_date] => 1978-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 16 [patent_no_of_words] => 39654 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/313/04313158.pdf [firstpage_image] =>[orig_patent_app_number] => 968049 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/968049
Cache apparatus for enabling overlap of instruction fetch operations Dec 10, 1978 Issued
Array ( [id] => 2057822 [patent_doc_number] => 04394725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-07-19 [patent_title] => 'Apparatus and method for transferring information units between processes in a multiprocessing system' [patent_app_type] => 1 [patent_app_number] => 5/966371 [patent_app_country] => US [patent_app_date] => 1978-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 97 [patent_no_of_words] => 55380 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/394/04394725.pdf [firstpage_image] =>[orig_patent_app_number] => 966371 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/966371
Apparatus and method for transferring information units between processes in a multiprocessing system Dec 3, 1978 Issued
Array ( [id] => 1910801 [patent_doc_number] => 04290113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-09-15 [patent_title] => 'Minicomputer' [patent_app_type] => 1 [patent_app_number] => 5/964930 [patent_app_country] => US [patent_app_date] => 1978-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2416 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/290/04290113.pdf [firstpage_image] =>[orig_patent_app_number] => 964930 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/964930
Minicomputer Nov 29, 1978 Issued
Array ( [id] => 1975715 [patent_doc_number] => 04354226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-12 [patent_title] => 'Communication terminal for interconnecting programmable controllers in a loop' [patent_app_type] => 1 [patent_app_number] => 5/960598 [patent_app_country] => US [patent_app_date] => 1978-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8083 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354226.pdf [firstpage_image] =>[orig_patent_app_number] => 960598 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/960598
Communication terminal for interconnecting programmable controllers in a loop Nov 13, 1978 Issued
Array ( [id] => 2017938 [patent_doc_number] => 04369494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-01-18 [patent_title] => 'Apparatus and method for providing synchronization between processes and events occurring at different times in a data processing system' [patent_app_type] => 1 [patent_app_number] => 5/959096 [patent_app_country] => US [patent_app_date] => 1978-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 62 [patent_no_of_words] => 33164 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/369/04369494.pdf [firstpage_image] =>[orig_patent_app_number] => 959096 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/959096
Apparatus and method for providing synchronization between processes and events occurring at different times in a data processing system Nov 8, 1978 Issued
Array ( [id] => 1988329 [patent_doc_number] => 04346452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-08-24 [patent_title] => 'NRZ/Biphase microcomputer serial communication logic' [patent_app_type] => 1 [patent_app_number] => 5/939743 [patent_app_country] => US [patent_app_date] => 1978-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 11505 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/346/04346452.pdf [firstpage_image] =>[orig_patent_app_number] => 939743 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/939743
NRZ/Biphase microcomputer serial communication logic Sep 4, 1978 Issued
Array ( [id] => 1900031 [patent_doc_number] => 04266270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-05-05 [patent_title] => 'Microprocessor having plural internal data buses' [patent_app_type] => 1 [patent_app_number] => 5/939741 [patent_app_country] => US [patent_app_date] => 1978-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 52 [patent_no_of_words] => 8609 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/266/04266270.pdf [firstpage_image] =>[orig_patent_app_number] => 939741 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/939741
Microprocessor having plural internal data buses Sep 4, 1978 Issued
Array ( [id] => 1967068 [patent_doc_number] => 04330842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-05-18 [patent_title] => 'Valid memory address pin elimination' [patent_app_type] => 1 [patent_app_number] => 5/939723 [patent_app_country] => US [patent_app_date] => 1978-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1413 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/330/04330842.pdf [firstpage_image] =>[orig_patent_app_number] => 939723 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/939723
Valid memory address pin elimination Sep 4, 1978 Issued
Array ( [id] => 1976700 [patent_doc_number] => 04365311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-12-21 [patent_title] => 'Control of instruction pipeline in data processing system' [patent_app_type] => 1 [patent_app_number] => 5/938346 [patent_app_country] => US [patent_app_date] => 1978-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4908 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/365/04365311.pdf [firstpage_image] =>[orig_patent_app_number] => 938346 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/938346
Control of instruction pipeline in data processing system Aug 30, 1978 Issued
Array ( [id] => 1913462 [patent_doc_number] => 04279020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-07-14 [patent_title] => 'Power supply circuit for a data processor' [patent_app_type] => 1 [patent_app_number] => 5/934817 [patent_app_country] => US [patent_app_date] => 1978-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2824 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/279/04279020.pdf [firstpage_image] =>[orig_patent_app_number] => 934817 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/934817
Power supply circuit for a data processor Aug 17, 1978 Issued
Array ( [id] => 1893125 [patent_doc_number] => 04267582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-05-12 [patent_title] => 'Circuit arrangement for storing a text' [patent_app_type] => 1 [patent_app_number] => 5/925276 [patent_app_country] => US [patent_app_date] => 1978-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3124 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/267/04267582.pdf [firstpage_image] =>[orig_patent_app_number] => 925276 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/925276
Circuit arrangement for storing a text Jul 16, 1978 Issued
Array ( [id] => 1886365 [patent_doc_number] => 04296467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1981-10-20 [patent_title] => 'Rotating chip selection technique and apparatus' [patent_app_type] => 1 [patent_app_number] => 5/921292 [patent_app_country] => US [patent_app_date] => 1978-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5288 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/296/04296467.pdf [firstpage_image] =>[orig_patent_app_number] => 921292 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/921292
Rotating chip selection technique and apparatus Jul 2, 1978 Issued
Array ( [id] => 2023556 [patent_doc_number] => 04373179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-02-08 [patent_title] => 'Dynamic address translation system' [patent_app_type] => 1 [patent_app_number] => 5/919173 [patent_app_country] => US [patent_app_date] => 1978-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4023 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/373/04373179.pdf [firstpage_image] =>[orig_patent_app_number] => 919173 [rel_patent_id] =>[rel_patent_doc_number] =>)
05/919173
Dynamic address translation system Jun 25, 1978 Issued
Menu