Rajnikant B. Patel

Array ( [id] => 15672443 [patent_doc_number] => 10600459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle [patent_app_type] => utility [patent_app_number] => 16/167340 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 16483 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14084303 [patent_doc_number] => 10238026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => System for monitoring and controlling activities of at least one gardening tool within at least one activity zone [patent_app_type] => utility [patent_app_number] => 16/140803 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7439 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13769543 [patent_doc_number] => 10177121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Package including a plurality of stacked semiconductor devices, an interposer and interface connections [patent_app_type] => utility [patent_app_number] => 16/132409 [patent_app_country] => US [patent_app_date] => 2018-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 8419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13799059 [patent_doc_number] => 20190013068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => MEMORY DEVICE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/130681 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13799061 [patent_doc_number] => 20190013069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => MEMORY DEVICE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/130682 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14177909 [patent_doc_number] => 10262975 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Package including a plurality of stacked semiconductor devices, an interposer and interface connections [patent_app_type] => utility [patent_app_number] => 16/130962 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 8418 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15624941 [patent_doc_number] => 20200082875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => METHOD FOR ASSISTING MEMORY CELL IN ACCESS OPERATION AND OPERATING MEMORY CELL, AND MEMORY DEVICE HAVING ASSIST CIRCUIT WITH PREDEFINED ASSIST STRENGTH [patent_app_type] => utility [patent_app_number] => 16/123459 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14078867 [patent_doc_number] => 20190088321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => OPERATING METHOD OF RESISTIVE MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 16/118445 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15672501 [patent_doc_number] => 10600489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Memory system, reading method, program, and memory controller [patent_app_type] => utility [patent_app_number] => 16/120093 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8209 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13989619 [patent_doc_number] => 20190063967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => METHOD AND APPARATUS FOR MULTI-CHANNEL SENSOR INTERFACE WITH PROGRAMMABLE GAIN, OFFSET AND BIAS [patent_app_type] => utility [patent_app_number] => 16/113845 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13629287 [patent_doc_number] => 20180366196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY [patent_app_type] => utility [patent_app_number] => 16/111746 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15641347 [patent_doc_number] => 10593678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-17 [patent_title] => Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/111499 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 13221 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13784941 [patent_doc_number] => 20190006009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => Three-dimensional Vertical NOR Flash Thin-Film Transistor Strings [patent_app_type] => utility [patent_app_number] => 16/107732 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -47 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15165891 [patent_doc_number] => 10488431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Real-time accelerometer calibration [patent_app_type] => utility [patent_app_number] => 15/999638 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 15169 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13921091 [patent_doc_number] => 10204669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Semiconductor system [patent_app_type] => utility [patent_app_number] => 16/054777 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 11561 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13861763 [patent_doc_number] => 10192604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/053608 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 78 [patent_no_of_words] => 39031 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053608 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13861761 [patent_doc_number] => 10192603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Method for controlling a semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/053578 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 78 [patent_no_of_words] => 39023 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14188877 [patent_doc_number] => 20190114144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => RANDOM CODE GENERATOR WITH DIFFERENTIAL CELLS AND ASSOCIATED CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/047343 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15474831 [patent_doc_number] => 10553298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-04 [patent_title] => Non-volatile memory with countermeasure for select gate disturb [patent_app_type] => utility [patent_app_number] => 16/047599 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 13896 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13558479 [patent_doc_number] => 20180330787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => MEMORY DEVICE INCLUDING DECODER FOR A PROGRAM PULSE AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/044280 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044280 [rel_patent_id] =>[rel_patent_doc_number] =>)