Search

Ralf T Seifert

Examiner (ID: 12518, Phone: (571)272-2657 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2902, 2914, 2904, 2900
Total Applications
7831
Issued Applications
7748
Pending Applications
0
Abandoned Applications
82

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4489253 [patent_doc_number] => 07884487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Rotation joint and semiconductor device having the same' [patent_app_type] => utility [patent_app_number] => 11/942483 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3275 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884487.pdf [firstpage_image] =>[orig_patent_app_number] => 11942483 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942483
Rotation joint and semiconductor device having the same Nov 18, 2007 Issued
Array ( [id] => 4749237 [patent_doc_number] => 20080157308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Multi-Die Semiconductor Package Structure and Method for Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 11/942174 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4872 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157308.pdf [firstpage_image] =>[orig_patent_app_number] => 11942174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942174
Multi-die semiconductor package structure and method for manufacturing the same Nov 18, 2007 Issued
Array ( [id] => 5407402 [patent_doc_number] => 20090121300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'MICROELECTRONIC IMAGER PACKAGES AND ASSOCIATED METHODS OF PACKAGING' [patent_app_type] => utility [patent_app_number] => 11/940184 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2513 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20090121300.pdf [firstpage_image] =>[orig_patent_app_number] => 11940184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940184
MICROELECTRONIC IMAGER PACKAGES AND ASSOCIATED METHODS OF PACKAGING Nov 13, 2007 Abandoned
Array ( [id] => 4896974 [patent_doc_number] => 20080116587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'CONDUCTOR POLYMER COMPOSITE CARRIER WITH ISOPROPERTY CONDUCTIVE COLUMNS' [patent_app_type] => utility [patent_app_number] => 11/938254 [patent_app_country] => US [patent_app_date] => 2007-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1827 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116587.pdf [firstpage_image] =>[orig_patent_app_number] => 11938254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/938254
CONDUCTOR POLYMER COMPOSITE CARRIER WITH ISOPROPERTY CONDUCTIVE COLUMNS Nov 9, 2007 Abandoned
Array ( [id] => 4820835 [patent_doc_number] => 20080122097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHOD OF FORMING METAL WIRING IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/935974 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122097.pdf [firstpage_image] =>[orig_patent_app_number] => 11935974 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935974
Method of forming metal wiring in semiconductor device Nov 5, 2007 Issued
Array ( [id] => 4489118 [patent_doc_number] => 07884458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package' [patent_app_type] => utility [patent_app_number] => 11/935953 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884458.pdf [firstpage_image] =>[orig_patent_app_number] => 11935953 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935953
Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package Nov 5, 2007 Issued
Array ( [id] => 5262286 [patent_doc_number] => 20090114971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS' [patent_app_type] => utility [patent_app_number] => 11/935143 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14301 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20090114971.pdf [firstpage_image] =>[orig_patent_app_number] => 11935143 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935143
CMOS EPROM and EEPROM devices and programmable CMOS inverters Nov 4, 2007 Issued
Array ( [id] => 4614343 [patent_doc_number] => 07989930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/924134 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3459 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989930.pdf [firstpage_image] =>[orig_patent_app_number] => 11924134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924134
Semiconductor package Oct 24, 2007 Issued
Array ( [id] => 4619138 [patent_doc_number] => 07998857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Integrated circuit and process for fabricating thereof' [patent_app_type] => utility [patent_app_number] => 11/923194 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4070 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/998/07998857.pdf [firstpage_image] =>[orig_patent_app_number] => 11923194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923194
Integrated circuit and process for fabricating thereof Oct 23, 2007 Issued
Array ( [id] => 4919336 [patent_doc_number] => 20080067648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Locking Feature and Method for Manufacturing Transfer Molded IC Packages' [patent_app_type] => utility [patent_app_number] => 11/856903 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067648.pdf [firstpage_image] =>[orig_patent_app_number] => 11856903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/856903
Locking feature and method for manufacturing transfer molded IC packages Sep 17, 2007 Issued
Array ( [id] => 7492400 [patent_doc_number] => 08030758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Semiconductor module and method for fabricating semiconductor module' [patent_app_type] => utility [patent_app_number] => 12/373024 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 17787 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030758.pdf [firstpage_image] =>[orig_patent_app_number] => 12373024 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/373024
Semiconductor module and method for fabricating semiconductor module Sep 12, 2007 Issued
Array ( [id] => 4479769 [patent_doc_number] => 07906853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Package structure for multiple die stack' [patent_app_type] => utility [patent_app_number] => 11/899523 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5291 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/906/07906853.pdf [firstpage_image] =>[orig_patent_app_number] => 11899523 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/899523
Package structure for multiple die stack Sep 5, 2007 Issued
11/849430 SUBSTRATE FOR USE IN SEMICONDUCTOR MANUFACTURING AND METHOD OF MAKING SAME Sep 3, 2007 Abandoned
Array ( [id] => 5016080 [patent_doc_number] => 20070259289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Thin film transistor array panel, manufacturing method thereof, and mask therefor' [patent_app_type] => utility [patent_app_number] => 11/824879 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 12692 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259289.pdf [firstpage_image] =>[orig_patent_app_number] => 11824879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/824879
Thin film transistor array panel, manufacturing method thereof, and mask therefor Jul 1, 2007 Issued
Array ( [id] => 4803176 [patent_doc_number] => 20080014764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE' [patent_app_type] => utility [patent_app_number] => 11/772623 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2958 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014764.pdf [firstpage_image] =>[orig_patent_app_number] => 11772623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772623
LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE Jul 1, 2007 Abandoned
Array ( [id] => 5340178 [patent_doc_number] => 20090178828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'HEAT DISSIPATING WIRING BOARD AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 12/300184 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20090178828.pdf [firstpage_image] =>[orig_patent_app_number] => 12300184 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/300184
Heat dissipating wiring board and method for manufacturing same Jun 12, 2007 Issued
95/000229 STACKED CHIP ASSEMBLY Feb 14, 2007 Issued
Array ( [id] => 5019395 [patent_doc_number] => 20070145361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'ORGANIC SEMICONDUCTOR MATERIAL AND ORGANIC ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/671085 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17854 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145361.pdf [firstpage_image] =>[orig_patent_app_number] => 11671085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671085
ORGANIC SEMICONDUCTOR MATERIAL AND ORGANIC ELECTRONIC DEVICE Feb 4, 2007 Abandoned
Array ( [id] => 5093033 [patent_doc_number] => 20070114642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Semiconductor device having a heat spreader exposed from a seal resin' [patent_app_type] => utility [patent_app_number] => 11/655253 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10737 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20070114642.pdf [firstpage_image] =>[orig_patent_app_number] => 11655253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655253
Semiconductor device having a heat spreader exposed from a seal resin Jan 18, 2007 Abandoned
Array ( [id] => 356602 [patent_doc_number] => 07489040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Interconnection structure of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/635495 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4571 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489040.pdf [firstpage_image] =>[orig_patent_app_number] => 11635495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635495
Interconnection structure of semiconductor device Dec 7, 2006 Issued
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