Ralf T Seifert
Examiner (ID: 12518, Phone: (571)272-2657 , Office: P/2914 )
Most Active Art Unit | 2914 |
Art Unit(s) | 2902, 2914, 2904, 2900 |
Total Applications | 7831 |
Issued Applications | 7748 |
Pending Applications | 0 |
Abandoned Applications | 82 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6996860
[patent_doc_number] => 20050136638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Low temperature sintering nanoparticle compositions'
[patent_app_type] => utility
[patent_app_number] => 10/739623
[patent_app_country] => US
[patent_app_date] => 2003-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3031
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0136/20050136638.pdf
[firstpage_image] =>[orig_patent_app_number] => 10739623
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/739623 | Low temperature sintering nanoparticle compositions | Dec 17, 2003 | Abandoned |
Array
(
[id] => 6994137
[patent_doc_number] => 20050133913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Stress distribution package'
[patent_app_type] => utility
[patent_app_number] => 10/738174
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6278
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20050133913.pdf
[firstpage_image] =>[orig_patent_app_number] => 10738174
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738174 | Stress distribution package | Dec 16, 2003 | Abandoned |
Array
(
[id] => 7198943
[patent_doc_number] => 20050051909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/736694
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5744
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20050051909.pdf
[firstpage_image] =>[orig_patent_app_number] => 10736694
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/736694 | Semiconductor device | Dec 16, 2003 | Issued |
Array
(
[id] => 7296669
[patent_doc_number] => 20040124956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Low-loss coplanar waveguides'
[patent_app_type] => new
[patent_app_number] => 10/734275
[patent_app_country] => US
[patent_app_date] => 2003-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3034
[patent_no_of_claims] => 91
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20040124956.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734275
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734275 | Low-loss coplanar waveguides | Dec 14, 2003 | Issued |
Array
(
[id] => 7094933
[patent_doc_number] => 20050127516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Small viatops for thick copper connectors'
[patent_app_type] => utility
[patent_app_number] => 10/735374
[patent_app_country] => US
[patent_app_date] => 2003-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3762
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20050127516.pdf
[firstpage_image] =>[orig_patent_app_number] => 10735374
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/735374 | Small viatops for thick copper connectors | Dec 11, 2003 | Abandoned |
Array
(
[id] => 418768
[patent_doc_number] => 07276440
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-02
[patent_title] => 'Method of fabrication of a die oxide ring'
[patent_app_type] => utility
[patent_app_number] => 10/734423
[patent_app_country] => US
[patent_app_date] => 2003-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2910
[patent_no_of_claims] => 7
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[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/276/07276440.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734423
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734423 | Method of fabrication of a die oxide ring | Dec 11, 2003 | Issued |
Array
(
[id] => 7448749
[patent_doc_number] => 20040164430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Circuit device and method of manufacture thereof'
[patent_app_type] => new
[patent_app_number] => 10/733724
[patent_app_country] => US
[patent_app_date] => 2003-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5589
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20040164430.pdf
[firstpage_image] =>[orig_patent_app_number] => 10733724
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/733724 | Circuit device and method of manufacture thereof | Dec 10, 2003 | Issued |
Array
(
[id] => 7094932
[patent_doc_number] => 20050127515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Sidewall sealing of porous dielectric materials'
[patent_app_type] => utility
[patent_app_number] => 10/732963
[patent_app_country] => US
[patent_app_date] => 2003-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5256
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20050127515.pdf
[firstpage_image] =>[orig_patent_app_number] => 10732963
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/732963 | Sidewall sealing of porous dielectric materials | Dec 10, 2003 | Issued |
Array
(
[id] => 7094886
[patent_doc_number] => 20050127489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Microelectronic device signal transmission by way of a lid'
[patent_app_type] => utility
[patent_app_number] => 10/733183
[patent_app_country] => US
[patent_app_date] => 2003-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3913
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20050127489.pdf
[firstpage_image] =>[orig_patent_app_number] => 10733183
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/733183 | Microelectronic device signal transmission by way of a lid | Dec 9, 2003 | Abandoned |
Array
(
[id] => 7448300
[patent_doc_number] => 20040164380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Semiconductor and semiconductor substrate, method of manufacturing the same, and semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/729983
[patent_app_country] => US
[patent_app_date] => 2003-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6581
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20040164380.pdf
[firstpage_image] =>[orig_patent_app_number] => 10729983
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/729983 | Semiconductor and semiconductor substrate, method of manufacturing the same, and semiconductor device | Dec 8, 2003 | Issued |
Array
(
[id] => 837343
[patent_doc_number] => 07394161
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-01
[patent_title] => 'Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto'
[patent_app_type] => utility
[patent_app_number] => 10/730834
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4807
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/394/07394161.pdf
[firstpage_image] =>[orig_patent_app_number] => 10730834
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/730834 | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto | Dec 7, 2003 | Issued |
Array
(
[id] => 7442110
[patent_doc_number] => 20040195669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Integrated circuit packaging apparatus and method'
[patent_app_type] => new
[patent_app_number] => 10/729734
[patent_app_country] => US
[patent_app_date] => 2003-12-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0195/20040195669.pdf
[firstpage_image] =>[orig_patent_app_number] => 10729734
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/729734 | Integrated circuit packaging apparatus and method | Dec 4, 2003 | Abandoned |
Array
(
[id] => 7169212
[patent_doc_number] => 20050121769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Stacked integrated circuit packages and methods of making the packages'
[patent_app_type] => utility
[patent_app_number] => 10/729544
[patent_app_country] => US
[patent_app_date] => 2003-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 10729544
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/729544 | Stacked integrated circuit packages and methods of making the packages | Dec 4, 2003 | Abandoned |
Array
(
[id] => 7169226
[patent_doc_number] => 20050121776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Integrated solder and heat spreader fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/729623
[patent_app_country] => US
[patent_app_date] => 2003-12-05
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[firstpage_image] =>[orig_patent_app_number] => 10729623
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/729623 | Integrated solder and heat spreader fabrication | Dec 4, 2003 | Abandoned |
Array
(
[id] => 7169191
[patent_doc_number] => 20050121764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Stackable integrated circuit packaging'
[patent_app_type] => utility
[patent_app_number] => 10/728324
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10728324
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728324 | Stackable integrated circuit packaging | Dec 3, 2003 | Issued |
Array
(
[id] => 7323519
[patent_doc_number] => 20040251555
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-16
[patent_title] => 'Interconnection structure of semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/725384
[patent_app_country] => US
[patent_app_date] => 2003-12-03
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0251/20040251555.pdf
[firstpage_image] =>[orig_patent_app_number] => 10725384
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725384 | Interconnection structure of semiconductor device | Dec 2, 2003 | Issued |
Array
(
[id] => 7429031
[patent_doc_number] => 20040161870
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-19
[patent_title] => 'Integrated micro electromechanical system encapsulation component and fabrication process of the component'
[patent_app_type] => new
[patent_app_number] => 10/725084
[patent_app_country] => US
[patent_app_date] => 2003-12-02
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[pdf_file] => publications/A1/0161/20040161870.pdf
[firstpage_image] =>[orig_patent_app_number] => 10725084
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725084 | Integrated micro electromechanical system encapsulation component and fabrication process of the component | Dec 1, 2003 | Issued |
Array
(
[id] => 7144243
[patent_doc_number] => 20050118781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Substrate, method of preparing a substrate, method of measurement, lithographic apparatus, device manufacturing method and device manufactured thereby, and machine-readable storage medium'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/724403 | Substrate, method of preparing a substrate, method of measurement, lithographic apparatus, device manufacturing method and device manufactured thereby, and machine-readable storage medium | Nov 30, 2003 | Issued |
Array
(
[id] => 703169
[patent_doc_number] => 07064434
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Customized microelectronic device and method for making customized electrical interconnections'
[patent_app_type] => utility
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10723103
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723103 | Customized microelectronic device and method for making customized electrical interconnections | Nov 25, 2003 | Issued |
Array
(
[id] => 6936557
[patent_doc_number] => 20050110118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Scribe seal providing enhanced substrate noise isolation'
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[patent_app_number] => 10/723114
[patent_app_country] => US
[patent_app_date] => 2003-11-26
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20050110118.pdf
[firstpage_image] =>[orig_patent_app_number] => 10723114
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723114 | Scribe seal providing enhanced substrate noise isolation | Nov 25, 2003 | Abandoned |