Ralf T Seifert

Array ( [id] => 7371964 [patent_doc_number] => 20040080036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'System in package structure' [patent_app_type] => new [patent_app_number] => 10/690743 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2682 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080036.pdf [firstpage_image] =>[orig_patent_app_number] => 10690743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 725915 [patent_doc_number] => 07045899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Semiconductor device and fabrication method of the same' [patent_app_type] => utility [patent_app_number] => 10/681283 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 137 [patent_no_of_words] => 11340 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045899.pdf [firstpage_image] =>[orig_patent_app_number] => 10681283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 586191 [patent_doc_number] => 07449771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-11 [patent_title] => 'Multiple leadframe laminated IC package' [patent_app_type] => utility [patent_app_number] => 10/681983 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 53 [patent_no_of_words] => 2486 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449771.pdf [firstpage_image] =>[orig_patent_app_number] => 10681983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7451980 [patent_doc_number] => 20040099961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/683814 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4042 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20040099961.pdf [firstpage_image] =>[orig_patent_app_number] => 10683814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7612381 [patent_doc_number] => 06903456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Package carrier having multiple individual ceramic substrates' [patent_app_type] => utility [patent_app_number] => 10/680893 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1295 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903456.pdf [firstpage_image] =>[orig_patent_app_number] => 10680893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7114411 [patent_doc_number] => 20050067711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Providing a via with an increased via contact area' [patent_app_type] => utility [patent_app_number] => 10/674704 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2531 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20050067711.pdf [firstpage_image] =>[orig_patent_app_number] => 10674704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 710798 [patent_doc_number] => 07056819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/673703 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2886 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/056/07056819.pdf [firstpage_image] =>[orig_patent_app_number] => 10673703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7604958 [patent_doc_number] => 07115972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Semiconductor device and chip-stack semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/670244 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 8301 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115972.pdf [firstpage_image] =>[orig_patent_app_number] => 10670244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 785781 [patent_doc_number] => 06989604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-24 [patent_title] => 'Conformal barrier liner in an integrated circuit interconnect' [patent_app_type] => utility [patent_app_number] => 10/672103 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4171 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989604.pdf [firstpage_image] =>[orig_patent_app_number] => 10672103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7278863 [patent_doc_number] => 20040061240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Semiconductor device and fabrication process thereof' [patent_app_type] => new [patent_app_number] => 10/668234 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6508 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061240.pdf [firstpage_image] =>[orig_patent_app_number] => 10668234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7434095 [patent_doc_number] => 20040065955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Apparatus and method of using thin film material as diffusion barrier for metallization' [patent_app_type] => new [patent_app_number] => 10/670413 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3208 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20040065955.pdf [firstpage_image] =>[orig_patent_app_number] => 10670413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7219805 [patent_doc_number] => 20040155322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Semiconductor package with pattern leads and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/667474 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20040155322.pdf [firstpage_image] =>[orig_patent_app_number] => 10667474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7371886 [patent_doc_number] => 20040080025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same' [patent_app_type] => new [patent_app_number] => 10/661484 [patent_app_country] => US [patent_app_date] => 2003-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7561 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080025.pdf [firstpage_image] =>[orig_patent_app_number] => 10661484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7295999 [patent_doc_number] => 20040124538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Multi-layer integrated semiconductor structure' [patent_app_type] => new [patent_app_number] => 10/655854 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7229 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124538.pdf [firstpage_image] =>[orig_patent_app_number] => 10655854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7411964 [patent_doc_number] => 20040207084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Multilayered cap barrier in microelectronic interconnect structures' [patent_app_type] => new [patent_app_number] => 10/648884 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4804 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207084.pdf [firstpage_image] =>[orig_patent_app_number] => 10648884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7397003 [patent_doc_number] => 20040104462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Semiconductor package' [patent_app_type] => new [patent_app_number] => 10/648363 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2008 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20040104462.pdf [firstpage_image] =>[orig_patent_app_number] => 10648363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700150 [patent_doc_number] => 07067859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Multi-layer staggered power bus layout design' [patent_app_type] => utility [patent_app_number] => 10/648054 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1250 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067859.pdf [firstpage_image] =>[orig_patent_app_number] => 10648054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 465329 [patent_doc_number] => 07239015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Heat sinks including nonlinear passageways' [patent_app_type] => utility [patent_app_number] => 10/647874 [patent_app_country] => US [patent_app_date] => 2003-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8297 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239015.pdf [firstpage_image] =>[orig_patent_app_number] => 10647874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 152649 [patent_doc_number] => 07679096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-16 [patent_title] => 'Integrated LED heat sink' [patent_app_type] => utility [patent_app_number] => 10/645474 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1822 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679096.pdf [firstpage_image] =>[orig_patent_app_number] => 10645474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7371909 [patent_doc_number] => 20040080028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Semiconductor device with semiconductor chip mounted in package' [patent_app_type] => new [patent_app_number] => 10/643717 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6329 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080028.pdf [firstpage_image] =>[orig_patent_app_number] => 10643717 [rel_patent_id] =>[rel_patent_doc_number] =>)