Ralf T Seifert

Array ( [id] => 7616709 [patent_doc_number] => 06946733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Ball grid array package having testing capability after mounting' [patent_app_type] => utility [patent_app_number] => 10/640073 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 939 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946733.pdf [firstpage_image] =>[orig_patent_app_number] => 10640073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7310128 [patent_doc_number] => 20040032016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Multi chip package' [patent_app_type] => new [patent_app_number] => 10/639633 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2109 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20040032016.pdf [firstpage_image] =>[orig_patent_app_number] => 10639633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 742854 [patent_doc_number] => 07030466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Intermediate structure for making integrated circuit device and wafer' [patent_app_type] => utility [patent_app_number] => 10/634404 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 6241 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030466.pdf [firstpage_image] =>[orig_patent_app_number] => 10634404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7022978 [patent_doc_number] => 20050017372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Semiconductor substrates including I/O redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same' [patent_app_type] => utility [patent_app_number] => 10/634123 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4865 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017372.pdf [firstpage_image] =>[orig_patent_app_number] => 10634123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7190009 [patent_doc_number] => 20040084780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit' [patent_app_type] => new [patent_app_number] => 10/630643 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20040084780.pdf [firstpage_image] =>[orig_patent_app_number] => 10630643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7612384 [patent_doc_number] => 06903453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Semiconductor integrated circuit device and debugger device for the same' [patent_app_type] => utility [patent_app_number] => 10/621654 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 9863 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903453.pdf [firstpage_image] =>[orig_patent_app_number] => 10621654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7120370 [patent_doc_number] => 20050012199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Folded flex circuit interconnect having a grid array interface' [patent_app_type] => utility [patent_app_number] => 10/623304 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6774 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20050012199.pdf [firstpage_image] =>[orig_patent_app_number] => 10623304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7352116 [patent_doc_number] => 20040012930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Microelectronic devices and methods for mounting microelectronic packages to circuit boards' [patent_app_type] => new [patent_app_number] => 10/621194 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4292 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012930.pdf [firstpage_image] =>[orig_patent_app_number] => 10621194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7086623 [patent_doc_number] => 20050006735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Die package' [patent_app_type] => utility [patent_app_number] => 10/616534 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2434 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20050006735.pdf [firstpage_image] =>[orig_patent_app_number] => 10616534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180464 [patent_doc_number] => 06744130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Isolated stripline structure' [patent_app_type] => B1 [patent_app_number] => 10/615063 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 598 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744130.pdf [firstpage_image] =>[orig_patent_app_number] => 10615063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7205033 [patent_doc_number] => 20040070051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Semiconductor device and method of manufacturing substrate' [patent_app_type] => new [patent_app_number] => 10/611157 [patent_app_country] => US [patent_app_date] => 2003-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20040070051.pdf [firstpage_image] =>[orig_patent_app_number] => 10611157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 703184 [patent_doc_number] => 07064442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-20 [patent_title] => 'Integrated circuit package device' [patent_app_type] => utility [patent_app_number] => 10/612274 [patent_app_country] => US [patent_app_date] => 2003-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064442.pdf [firstpage_image] =>[orig_patent_app_number] => 10612274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 708775 [patent_doc_number] => 07061109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Semiconductor substrate-based BGA interconnection for testing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/602253 [patent_app_country] => US [patent_app_date] => 2003-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 4525 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061109.pdf [firstpage_image] =>[orig_patent_app_number] => 10602253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7386440 [patent_doc_number] => 20040021149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Pressure-contact type semiconductor device' [patent_app_type] => new [patent_app_number] => 10/460414 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6652 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20040021149.pdf [firstpage_image] =>[orig_patent_app_number] => 10460414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7427713 [patent_doc_number] => 20040007774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Semiconductor chip carrier affording a high-density external interface' [patent_app_type] => new [patent_app_number] => 10/455812 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 91 [patent_figures_cnt] => 91 [patent_no_of_words] => 22510 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20040007774.pdf [firstpage_image] =>[orig_patent_app_number] => 10455812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6723441 [patent_doc_number] => 20030205753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/454316 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3603 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205753.pdf [firstpage_image] =>[orig_patent_app_number] => 10454316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 746729 [patent_doc_number] => 07026712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Peltier module with durable power supply lines and exothermic module with built-in cooler' [patent_app_type] => utility [patent_app_number] => 10/436165 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6003 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026712.pdf [firstpage_image] =>[orig_patent_app_number] => 10436165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1047234 [patent_doc_number] => 06864513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Light emitting diode bulb having high heat dissipating efficiency' [patent_app_type] => utility [patent_app_number] => 10/431013 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864513.pdf [firstpage_image] =>[orig_patent_app_number] => 10431013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6676934 [patent_doc_number] => 20030227074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/420744 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2075 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227074.pdf [firstpage_image] =>[orig_patent_app_number] => 10420744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6807319 [patent_doc_number] => 20030197258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Integrated circuit device packaging structure and packaging method' [patent_app_type] => new [patent_app_number] => 10/418204 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3165 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197258.pdf [firstpage_image] =>[orig_patent_app_number] => 10418204 [rel_patent_id] =>[rel_patent_doc_number] =>)