Ralf T Seifert
Examiner (ID: 12518, Phone: (571)272-2657 , Office: P/2914 )
Most Active Art Unit | 2914 |
Art Unit(s) | 2902, 2914, 2904, 2900 |
Total Applications | 7831 |
Issued Applications | 7748 |
Pending Applications | 0 |
Abandoned Applications | 82 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6733442
[patent_doc_number] => 20030011077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-16
[patent_title] => 'Sealing resin for flip-flop mounting'
[patent_app_type] => new
[patent_app_number] => 10/204523
[patent_app_country] => US
[patent_app_date] => 2002-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2746
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20030011077.pdf
[firstpage_image] =>[orig_patent_app_number] => 10204523
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/204523 | Sealing resin for flip-flop mounting | Aug 20, 2002 | Abandoned |
Array
(
[id] => 1022597
[patent_doc_number] => 06888245
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/222814
[patent_app_country] => US
[patent_app_date] => 2002-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 24
[patent_no_of_words] => 6104
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/888/06888245.pdf
[firstpage_image] =>[orig_patent_app_number] => 10222814
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/222814 | Semiconductor device | Aug 18, 2002 | Issued |
Array
(
[id] => 6690913
[patent_doc_number] => 20030038345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-27
[patent_title] => 'IC package substrate with over voltage protection function'
[patent_app_type] => new
[patent_app_number] => 10/219514
[patent_app_country] => US
[patent_app_date] => 2002-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1528
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20030038345.pdf
[firstpage_image] =>[orig_patent_app_number] => 10219514
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/219514 | IC package substrate with over voltage protection function | Aug 14, 2002 | Issued |
Array
(
[id] => 6755846
[patent_doc_number] => 20030003623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-02
[patent_title] => 'Electronic component mounted on a flat substrate and padded with a fluid filler'
[patent_app_type] => new
[patent_app_number] => 10/219515
[patent_app_country] => US
[patent_app_date] => 2002-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1667
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20030003623.pdf
[firstpage_image] =>[orig_patent_app_number] => 10219515
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/219515 | Electronic component mounted on a flat substrate and padded with a fluid filler | Aug 14, 2002 | Issued |
Array
(
[id] => 6854209
[patent_doc_number] => 20030127710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => 'Low-loss coplanar waveguides and method of fabrication'
[patent_app_type] => new
[patent_app_number] => 10/206205
[patent_app_country] => US
[patent_app_date] => 2002-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3034
[patent_no_of_claims] => 91
[patent_no_of_ind_claims] => 7
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20030127710.pdf
[firstpage_image] =>[orig_patent_app_number] => 10206205
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/206205 | Low-loss coplanar waveguides and method of fabrication | Jul 28, 2002 | Issued |
Array
(
[id] => 7348442
[patent_doc_number] => 20040012092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-22
[patent_title] => 'Apparatus and method for reducing interference between signal lines'
[patent_app_type] => new
[patent_app_number] => 10/200093
[patent_app_country] => US
[patent_app_date] => 2002-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1703
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20040012092.pdf
[firstpage_image] =>[orig_patent_app_number] => 10200093
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/200093 | Apparatus and method for reducing interference between signal lines | Jul 18, 2002 | Abandoned |
Array
(
[id] => 1120910
[patent_doc_number] => 06798051
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-28
[patent_title] => 'Connection of packaged integrated memory chips to a printed circuit board'
[patent_app_type] => B2
[patent_app_number] => 10/197793
[patent_app_country] => US
[patent_app_date] => 2002-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4332
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/798/06798051.pdf
[firstpage_image] =>[orig_patent_app_number] => 10197793
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197793 | Connection of packaged integrated memory chips to a printed circuit board | Jul 17, 2002 | Issued |
Array
(
[id] => 1241557
[patent_doc_number] => 06683380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-27
[patent_title] => 'Integrated circuit with bonding layer over active circuitry'
[patent_app_type] => B2
[patent_app_number] => 10/191453
[patent_app_country] => US
[patent_app_date] => 2002-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 3596
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/683/06683380.pdf
[firstpage_image] =>[orig_patent_app_number] => 10191453
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/191453 | Integrated circuit with bonding layer over active circuitry | Jul 9, 2002 | Issued |
Array
(
[id] => 7427750
[patent_doc_number] => 20040007780
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'Particle-filled semiconductor attachment material'
[patent_app_type] => new
[patent_app_number] => 10/192004
[patent_app_country] => US
[patent_app_date] => 2002-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2138
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20040007780.pdf
[firstpage_image] =>[orig_patent_app_number] => 10192004
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/192004 | Particle-filled semiconductor attachment material | Jul 8, 2002 | Abandoned |
Array
(
[id] => 1169877
[patent_doc_number] => 06756671
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-29
[patent_title] => 'Microelectronic device with a redistribution layer having a step shaped portion and method of making the same'
[patent_app_type] => B2
[patent_app_number] => 10/190274
[patent_app_country] => US
[patent_app_date] => 2002-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 5653
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/756/06756671.pdf
[firstpage_image] =>[orig_patent_app_number] => 10190274
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/190274 | Microelectronic device with a redistribution layer having a step shaped portion and method of making the same | Jul 4, 2002 | Issued |
Array
(
[id] => 6635888
[patent_doc_number] => 20030006498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'Semiconductor integrated circuit device, mounting board, and device and board assembly'
[patent_app_type] => new
[patent_app_number] => 10/188083
[patent_app_country] => US
[patent_app_date] => 2002-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 6102
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20030006498.pdf
[firstpage_image] =>[orig_patent_app_number] => 10188083
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/188083 | Semiconductor integrated circuit device, mounting board, and device and board assembly | Jul 2, 2002 | Issued |
Array
(
[id] => 7420428
[patent_doc_number] => 20040000579
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-01
[patent_title] => 'Forming contact arrays on substrates'
[patent_app_type] => new
[patent_app_number] => 10/186774
[patent_app_country] => US
[patent_app_date] => 2002-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20040000579.pdf
[firstpage_image] =>[orig_patent_app_number] => 10186774
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/186774 | Forming contact arrays on substrates | Jun 30, 2002 | Abandoned |
Array
(
[id] => 1034466
[patent_doc_number] => 06875675
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-05
[patent_title] => 'Method for manufacturing a semiconductor film having a planarized surface'
[patent_app_type] => utility
[patent_app_number] => 10/186354
[patent_app_country] => US
[patent_app_date] => 2002-06-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/875/06875675.pdf
[firstpage_image] =>[orig_patent_app_number] => 10186354
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/186354 | Method for manufacturing a semiconductor film having a planarized surface | Jun 27, 2002 | Issued |
Array
(
[id] => 1107771
[patent_doc_number] => 06809030
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-26
[patent_title] => 'Method and structure for controlling the interface roughness of cobalt disilicide'
[patent_app_type] => B2
[patent_app_number] => 10/185547
[patent_app_country] => US
[patent_app_date] => 2002-06-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/809/06809030.pdf
[firstpage_image] =>[orig_patent_app_number] => 10185547
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/185547 | Method and structure for controlling the interface roughness of cobalt disilicide | Jun 27, 2002 | Issued |
Array
(
[id] => 7421239
[patent_doc_number] => 20040000709
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-01
[patent_title] => 'Internal package interconnect with electrically parallel vias'
[patent_app_type] => new
[patent_app_number] => 10/183274
[patent_app_country] => US
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[pdf_file] => publications/A1/0000/20040000709.pdf
[firstpage_image] =>[orig_patent_app_number] => 10183274
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/183274 | Internal package interconnect with electrically parallel vias | Jun 25, 2002 | Abandoned |
Array
(
[id] => 6823656
[patent_doc_number] => 20030234277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'Microelectronic device interconnects'
[patent_app_type] => new
[patent_app_number] => 10/183874
[patent_app_country] => US
[patent_app_date] => 2002-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20030234277.pdf
[firstpage_image] =>[orig_patent_app_number] => 10183874
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/183874 | Microelectronic device interconnects | Jun 24, 2002 | Issued |
Array
(
[id] => 1159885
[patent_doc_number] => 06762504
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-13
[patent_title] => 'Release films and adhesive films using the release films'
[patent_app_type] => B1
[patent_app_number] => 10/172383
[patent_app_country] => US
[patent_app_date] => 2002-06-14
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/762/06762504.pdf
[firstpage_image] =>[orig_patent_app_number] => 10172383
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172383 | Release films and adhesive films using the release films | Jun 13, 2002 | Issued |
Array
(
[id] => 1277084
[patent_doc_number] => 06650015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-18
[patent_title] => 'Cavity-down ball grid array package with semiconductor chip solder ball'
[patent_app_type] => B2
[patent_app_number] => 10/173213
[patent_app_country] => US
[patent_app_date] => 2002-06-14
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/650/06650015.pdf
[firstpage_image] =>[orig_patent_app_number] => 10173213
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/173213 | Cavity-down ball grid array package with semiconductor chip solder ball | Jun 13, 2002 | Issued |
Array
(
[id] => 996892
[patent_doc_number] => 06914334
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Circuit board with trace configuration for high-speed digital differential signaling'
[patent_app_type] => utility
[patent_app_number] => 10/167904
[patent_app_country] => US
[patent_app_date] => 2002-06-12
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/914/06914334.pdf
[firstpage_image] =>[orig_patent_app_number] => 10167904
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/167904 | Circuit board with trace configuration for high-speed digital differential signaling | Jun 11, 2002 | Issued |
Array
(
[id] => 6753471
[patent_doc_number] => 20030001247
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-02
[patent_title] => 'High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing'
[patent_app_type] => new
[patent_app_number] => 10/170854
[patent_app_country] => US
[patent_app_date] => 2002-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20030001247.pdf
[firstpage_image] =>[orig_patent_app_number] => 10170854
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/170854 | High voltage semiconductor device housing with increased clearance between housing can and die for improved flux flushing | Jun 11, 2002 | Issued |