Search

Ralf T Seifert

Examiner (ID: 12518, Phone: (571)272-2657 , Office: P/2914 )

Most Active Art Unit
2914
Art Unit(s)
2902, 2914, 2904, 2900
Total Applications
7831
Issued Applications
7748
Pending Applications
0
Abandoned Applications
82

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4624775 [patent_doc_number] => 08004076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Microelectronic package with carbon nanotubes interconnect and method of making same' [patent_app_type] => utility [patent_app_number] => 12/242361 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2790 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004076.pdf [firstpage_image] =>[orig_patent_app_number] => 12242361 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242361
Microelectronic package with carbon nanotubes interconnect and method of making same Sep 29, 2008 Issued
Array ( [id] => 6359034 [patent_doc_number] => 20100078818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'DIFFUSION BARRIER AND ADHESION LAYER FOR AN INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/242416 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20100078818.pdf [firstpage_image] =>[orig_patent_app_number] => 12242416 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242416
Diffusion barrier and adhesion layer for an interconnect structure Sep 29, 2008 Issued
Array ( [id] => 7975413 [patent_doc_number] => 08070452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Blade provided with a horizontally-wound spar, and a method of fabricating such a spar' [patent_app_type] => utility [patent_app_number] => 12/144676 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 3720 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/070/08070452.pdf [firstpage_image] =>[orig_patent_app_number] => 12144676 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144676
Blade provided with a horizontally-wound spar, and a method of fabricating such a spar Jun 23, 2008 Issued
Array ( [id] => 4663707 [patent_doc_number] => 20080254614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/143918 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254614.pdf [firstpage_image] =>[orig_patent_app_number] => 12143918 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143918
Multilayered cap barrier in microelectronic interconnect structures Jun 22, 2008 Issued
Array ( [id] => 217470 [patent_doc_number] => 07612382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Method for defeating reverse engineering of integrated circuits by optical means' [patent_app_type] => utility [patent_app_number] => 12/140714 [patent_app_country] => US [patent_app_date] => 2008-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6890 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/612/07612382.pdf [firstpage_image] =>[orig_patent_app_number] => 12140714 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/140714
Method for defeating reverse engineering of integrated circuits by optical means Jun 16, 2008 Issued
Array ( [id] => 4817067 [patent_doc_number] => 20080224326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Chip structure with bumps and testing pads' [patent_app_type] => utility [patent_app_number] => 12/127794 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20080224326.pdf [firstpage_image] =>[orig_patent_app_number] => 12127794 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127794
Chip structure with bumps and testing pads May 26, 2008 Issued
Array ( [id] => 4722971 [patent_doc_number] => 20080202792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS' [patent_app_type] => utility [patent_app_number] => 12/113195 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5730 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20080202792.pdf [firstpage_image] =>[orig_patent_app_number] => 12113195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/113195
INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS Apr 29, 2008 Abandoned
Array ( [id] => 4532715 [patent_doc_number] => 07923849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Interconnections for flip-chip using lead-free solders and having reaction barrier layers' [patent_app_type] => utility [patent_app_number] => 12/113152 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 5738 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/923/07923849.pdf [firstpage_image] =>[orig_patent_app_number] => 12113152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/113152
Interconnections for flip-chip using lead-free solders and having reaction barrier layers Apr 29, 2008 Issued
Array ( [id] => 124133 [patent_doc_number] => 07705431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-27 [patent_title] => 'Method of improving adhesion between two dielectric films' [patent_app_type] => utility [patent_app_number] => 12/060344 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/705/07705431.pdf [firstpage_image] =>[orig_patent_app_number] => 12060344 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060344
Method of improving adhesion between two dielectric films Mar 31, 2008 Issued
Array ( [id] => 32574 [patent_doc_number] => 07790614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/030960 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4925 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790614.pdf [firstpage_image] =>[orig_patent_app_number] => 12030960 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030960
Semiconductor device and method of manufacturing the same Feb 13, 2008 Issued
Array ( [id] => 4915761 [patent_doc_number] => 20080096361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'STRUCTURE FOR REALIZING INTEGRATED CIRCUIT HAVING SCHOTTKY DIODE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/963354 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3253 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20080096361.pdf [firstpage_image] =>[orig_patent_app_number] => 11963354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963354
Structure for realizing integrated circuit having Schottky diode and method of fabricating the same Dec 20, 2007 Issued
Array ( [id] => 4749257 [patent_doc_number] => 20080157328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 11/960760 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4460 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157328.pdf [firstpage_image] =>[orig_patent_app_number] => 11960760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960760
Method of making a multi-layered semiconductor device Dec 19, 2007 Issued
Array ( [id] => 5327991 [patent_doc_number] => 20090108468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/953134 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4042 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108468.pdf [firstpage_image] =>[orig_patent_app_number] => 11953134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953134
Stacked semiconductor package and method for manufacturing the same Dec 9, 2007 Issued
Array ( [id] => 4577861 [patent_doc_number] => 07833831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Method of manufacturing an electronic component and an electronic device' [patent_app_type] => utility [patent_app_number] => 11/951693 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5324 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/833/07833831.pdf [firstpage_image] =>[orig_patent_app_number] => 11951693 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951693
Method of manufacturing an electronic component and an electronic device Dec 5, 2007 Issued
Array ( [id] => 4829438 [patent_doc_number] => 20080128882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/949523 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128882.pdf [firstpage_image] =>[orig_patent_app_number] => 11949523 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949523
CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE SAME Dec 2, 2007 Abandoned
Array ( [id] => 5573071 [patent_doc_number] => 20090140432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'PAD STRUCTURE TO PROVIDE IMPROVED STRESS RELIEF' [patent_app_type] => utility [patent_app_number] => 11/947184 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1830 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140432.pdf [firstpage_image] =>[orig_patent_app_number] => 11947184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947184
Pad structure to provide improved stress relief Nov 28, 2007 Issued
Array ( [id] => 4782695 [patent_doc_number] => 20080136024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/947393 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5364 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136024.pdf [firstpage_image] =>[orig_patent_app_number] => 11947393 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947393
SEMICONDUCTOR DEVICE Nov 28, 2007 Abandoned
Array ( [id] => 4433604 [patent_doc_number] => 07969016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Self-aligned wafer or chip structure, and self-aligned stacked structure' [patent_app_type] => utility [patent_app_number] => 11/946814 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 4861 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969016.pdf [firstpage_image] =>[orig_patent_app_number] => 11946814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946814
Self-aligned wafer or chip structure, and self-aligned stacked structure Nov 27, 2007 Issued
Array ( [id] => 4499701 [patent_doc_number] => 07948092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Electronic component and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/943203 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5084 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948092.pdf [firstpage_image] =>[orig_patent_app_number] => 11943203 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943203
Electronic component and method for manufacturing the same Nov 19, 2007 Issued
Array ( [id] => 112295 [patent_doc_number] => 07713783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Electronic component package, electronic component using the package, and method for manufacturing electronic component package' [patent_app_type] => utility [patent_app_number] => 11/942203 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4451 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/713/07713783.pdf [firstpage_image] =>[orig_patent_app_number] => 11942203 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942203
Electronic component package, electronic component using the package, and method for manufacturing electronic component package Nov 18, 2007 Issued
Menu