Search

Ramon A. Mercado

Examiner (ID: 5601, Phone: (571)270-5744 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 3658, 2132, 2186
Total Applications
468
Issued Applications
375
Pending Applications
16
Abandoned Applications
78

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6424900 [patent_doc_number] => 20020184457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Receiving apparatus that receives and accumulates broadcast contents and makes contents available according to user requests' [patent_app_type] => new [patent_app_number] => 09/867117 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 25016 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184457.pdf [firstpage_image] =>[orig_patent_app_number] => 09867117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867117
Receiving apparatus that receives and accumulates broadcast contents and makes contents available according to user requests May 28, 2001 Issued
Array ( [id] => 6424847 [patent_doc_number] => 20020184452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Embedded memory access method and system for application specific integrated circuits' [patent_app_type] => new [patent_app_number] => 09/867957 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3618 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184452.pdf [firstpage_image] =>[orig_patent_app_number] => 09867957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867957
Embedded memory access method and system for application specific integrated circuits May 28, 2001 Issued
Array ( [id] => 6424651 [patent_doc_number] => 20020184437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Memory architecture for supporting concurrent access of different types' [patent_app_type] => new [patent_app_number] => 09/870361 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2066 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184437.pdf [firstpage_image] =>[orig_patent_app_number] => 09870361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870361
Memory architecture for supporting concurrent access of different types May 28, 2001 Issued
Array ( [id] => 6423455 [patent_doc_number] => 20020184328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Chip multiprocessor with multiple operating systems' [patent_app_type] => new [patent_app_number] => 09/865605 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184328.pdf [firstpage_image] =>[orig_patent_app_number] => 09865605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865605
Chip multiprocessor with multiple operating systems May 28, 2001 Issued
Array ( [id] => 5971433 [patent_doc_number] => 20020091901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Disk caching' [patent_app_type] => new [patent_app_number] => 09/866509 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091901.pdf [firstpage_image] =>[orig_patent_app_number] => 09866509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866509
Method for caching information between work sessions May 24, 2001 Issued
Array ( [id] => 6460337 [patent_doc_number] => 20020178325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method and apparatus for scalable error correction code generation performance' [patent_app_type] => new [patent_app_number] => 09/866110 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4515 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178325.pdf [firstpage_image] =>[orig_patent_app_number] => 09866110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866110
Method and apparatus for scalable error correction code generation performance May 24, 2001 Issued
Array ( [id] => 1376907 [patent_doc_number] => 06578112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Cache memory control device for multi-processor system' [patent_app_type] => B2 [patent_app_number] => 09/864328 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11509 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578112.pdf [firstpage_image] =>[orig_patent_app_number] => 09864328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864328
Cache memory control device for multi-processor system May 24, 2001 Issued
Array ( [id] => 999046 [patent_doc_number] => 06915396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Fast priority determination circuit with rotating priority' [patent_app_type] => utility [patent_app_number] => 09/853738 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8259 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915396.pdf [firstpage_image] =>[orig_patent_app_number] => 09853738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853738
Fast priority determination circuit with rotating priority May 9, 2001 Issued
Array ( [id] => 1100407 [patent_doc_number] => 06823441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of multiplexed address and data bus' [patent_app_type] => B1 [patent_app_number] => 09/838975 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4404 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823441.pdf [firstpage_image] =>[orig_patent_app_number] => 09838975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838975
Method of multiplexed address and data bus Apr 19, 2001 Issued
Array ( [id] => 6001613 [patent_doc_number] => 20020029308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Method for emulating hardware features of a foreign architecture in a host operating system environment' [patent_app_type] => new [patent_app_number] => 09/838530 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4036 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20020029308.pdf [firstpage_image] =>[orig_patent_app_number] => 09838530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838530
Method for emulating hardware features of a foreign architecture in a host operating system environment Apr 17, 2001 Issued
Array ( [id] => 6763002 [patent_doc_number] => 20030126364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Arrangement and method for reducing the processing time of a data processing device' [patent_app_type] => new [patent_app_number] => 10/204421 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1841 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126364.pdf [firstpage_image] =>[orig_patent_app_number] => 10204421 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/204421
Arrangement and method for reducing the processing time of a data processing device Mar 19, 2001 Issued
Array ( [id] => 6881009 [patent_doc_number] => 20010032297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Cache memory apparatus and data processing system' [patent_app_type] => new [patent_app_number] => 09/797599 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3469 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032297.pdf [firstpage_image] =>[orig_patent_app_number] => 09797599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797599
Cache memory apparatus and data processing system Mar 4, 2001 Abandoned
Array ( [id] => 1240839 [patent_doc_number] => 06691205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Method for using RAM buffers with simultaneous accesses in flash based storage systems' [patent_app_type] => B2 [patent_app_number] => 09/797580 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3469 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691205.pdf [firstpage_image] =>[orig_patent_app_number] => 09797580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797580
Method for using RAM buffers with simultaneous accesses in flash based storage systems Mar 4, 2001 Issued
Array ( [id] => 7622379 [patent_doc_number] => 06687787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Configuration of a data storage system' [patent_app_type] => B1 [patent_app_number] => 09/800091 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687787.pdf [firstpage_image] =>[orig_patent_app_number] => 09800091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800091
Configuration of a data storage system Mar 4, 2001 Issued
Array ( [id] => 1311352 [patent_doc_number] => 06625709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Fair share dynamic resource allocation scheme with a safety buffer' [patent_app_type] => B2 [patent_app_number] => 09/798492 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9215 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625709.pdf [firstpage_image] =>[orig_patent_app_number] => 09798492 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798492
Fair share dynamic resource allocation scheme with a safety buffer Mar 1, 2001 Issued
Array ( [id] => 1385883 [patent_doc_number] => 06571318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism' [patent_app_type] => B1 [patent_app_number] => 09/798469 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 15274 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571318.pdf [firstpage_image] =>[orig_patent_app_number] => 09798469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798469
Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism Mar 1, 2001 Issued
Array ( [id] => 7622363 [patent_doc_number] => 06687803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Processor architecture and a method of processing' [patent_app_type] => B1 [patent_app_number] => 09/798130 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2773 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687803.pdf [firstpage_image] =>[orig_patent_app_number] => 09798130 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798130
Processor architecture and a method of processing Mar 1, 2001 Issued
Array ( [id] => 1431895 [patent_doc_number] => 06516394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'System and method for management of storage devices using labels' [patent_app_type] => B1 [patent_app_number] => 09/798580 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4986 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516394.pdf [firstpage_image] =>[orig_patent_app_number] => 09798580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798580
System and method for management of storage devices using labels Mar 1, 2001 Issued
Array ( [id] => 1337103 [patent_doc_number] => 06604175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Data cache and method of storing data by assigning each independently cached area in the cache to store data associated with one item type' [patent_app_type] => B2 [patent_app_number] => 09/797458 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4459 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604175.pdf [firstpage_image] =>[orig_patent_app_number] => 09797458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797458
Data cache and method of storing data by assigning each independently cached area in the cache to store data associated with one item type Feb 28, 2001 Issued
Array ( [id] => 6451285 [patent_doc_number] => 20020129212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Virtualized NVRAM access methods to provide NVRAM chrp regions for logical partitions through hypervisor system calls' [patent_app_type] => new [patent_app_number] => 09/798292 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3199 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129212.pdf [firstpage_image] =>[orig_patent_app_number] => 09798292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798292
Virtualized NVRAM access methods to provide NVRAM CHRP regions for logical partitions through hypervisor system calls Feb 28, 2001 Issued
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