Search

Ramon A. Mercado

Examiner (ID: 5601, Phone: (571)270-5744 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 3658, 2132, 2186
Total Applications
468
Issued Applications
375
Pending Applications
16
Abandoned Applications
78

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 645520 [patent_doc_number] => 07124253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Supporting directory-based cache coherence in an object-addressed memory hierarchy' [patent_app_type] => utility [patent_app_number] => 10/782147 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3302 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124253.pdf [firstpage_image] =>[orig_patent_app_number] => 10782147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782147
Supporting directory-based cache coherence in an object-addressed memory hierarchy Feb 17, 2004 Issued
Array ( [id] => 609493 [patent_doc_number] => 07155582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Dynamic reordering of memory requests' [patent_app_type] => utility [patent_app_number] => 10/779705 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8448 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155582.pdf [firstpage_image] =>[orig_patent_app_number] => 10779705 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779705
Dynamic reordering of memory requests Feb 17, 2004 Issued
Array ( [id] => 7193445 [patent_doc_number] => 20050193240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Dynamic reconfiguration of memory in a multi-cluster storage control unit' [patent_app_type] => utility [patent_app_number] => 10/781467 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2679 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20050193240.pdf [firstpage_image] =>[orig_patent_app_number] => 10781467 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781467
Dynamic reconfiguration of memory in a multi-cluster storage control unit Feb 16, 2004 Issued
Array ( [id] => 7605727 [patent_doc_number] => 07099995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Metadata access during error handling routines' [patent_app_type] => utility [patent_app_number] => 10/781200 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2571 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/099/07099995.pdf [firstpage_image] =>[orig_patent_app_number] => 10781200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781200
Metadata access during error handling routines Feb 16, 2004 Issued
Array ( [id] => 666967 [patent_doc_number] => 07103740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'Backup mechanism for a multi-class file system' [patent_app_type] => utility [patent_app_number] => 10/749334 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 20985 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103740.pdf [firstpage_image] =>[orig_patent_app_number] => 10749334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749334
Backup mechanism for a multi-class file system Dec 30, 2003 Issued
Array ( [id] => 7261918 [patent_doc_number] => 20050144374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Hardware detected command-per-clock' [patent_app_type] => utility [patent_app_number] => 10/749183 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1136 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144374.pdf [firstpage_image] =>[orig_patent_app_number] => 10749183 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749183
Hardware detected command-per-clock Dec 29, 2003 Issued
Array ( [id] => 690694 [patent_doc_number] => 07080212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-18 [patent_title] => 'Closed loop adaptive prestage method, system, and product for prestaging cache blocks' [patent_app_type] => utility [patent_app_number] => 10/750101 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3817 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080212.pdf [firstpage_image] =>[orig_patent_app_number] => 10750101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/750101
Closed loop adaptive prestage method, system, and product for prestaging cache blocks Dec 28, 2003 Issued
Array ( [id] => 637493 [patent_doc_number] => 07130965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Apparatus and method for store address for store address prefetch and line locking' [patent_app_type] => utility [patent_app_number] => 10/743134 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3704 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130965.pdf [firstpage_image] =>[orig_patent_app_number] => 10743134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/743134
Apparatus and method for store address for store address prefetch and line locking Dec 22, 2003 Issued
Array ( [id] => 705044 [patent_doc_number] => 07069382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Method of RAID 5 write hole prevention' [patent_app_type] => utility [patent_app_number] => 10/743048 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2892 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069382.pdf [firstpage_image] =>[orig_patent_app_number] => 10743048 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/743048
Method of RAID 5 write hole prevention Dec 22, 2003 Issued
Array ( [id] => 6999625 [patent_doc_number] => 20050138314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Write-protected micro memory device' [patent_app_type] => utility [patent_app_number] => 10/743144 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3139 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138314.pdf [firstpage_image] =>[orig_patent_app_number] => 10743144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/743144
Write-protected micro memory device Dec 22, 2003 Abandoned
Array ( [id] => 5160987 [patent_doc_number] => 20070174031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method and device for taking an access control policy decision' [patent_app_type] => utility [patent_app_number] => 10/596769 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8713 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174031.pdf [firstpage_image] =>[orig_patent_app_number] => 10596769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/596769
Method and device for taking an access control policy decision Dec 22, 2003 Abandoned
Array ( [id] => 7013514 [patent_doc_number] => 20050066138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Multiple storage element command queues' [patent_app_type] => utility [patent_app_number] => 10/742949 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2946 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066138.pdf [firstpage_image] =>[orig_patent_app_number] => 10742949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742949
Multiple storage element command queues Dec 22, 2003 Issued
Array ( [id] => 7440277 [patent_doc_number] => 20040162950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Non-volatile mass storage cache coherency apparatus' [patent_app_type] => new [patent_app_number] => 10/740633 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20040162950.pdf [firstpage_image] =>[orig_patent_app_number] => 10740633 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/740633
Non-volatile mass storage cache coherency apparatus Dec 21, 2003 Issued
Array ( [id] => 7341400 [patent_doc_number] => 20040133761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Systems and methods for avoiding base address collisions using alternate components' [patent_app_type] => new [patent_app_number] => 10/719781 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9281 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133761.pdf [firstpage_image] =>[orig_patent_app_number] => 10719781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/719781
Systems and methods for avoiding base address collisions using alternate components Nov 20, 2003 Issued
Array ( [id] => 1020899 [patent_doc_number] => 06892271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Memory module resync' [patent_app_type] => utility [patent_app_number] => 10/690139 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14481 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892271.pdf [firstpage_image] =>[orig_patent_app_number] => 10690139 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690139
Memory module resync Oct 20, 2003 Issued
Array ( [id] => 666961 [patent_doc_number] => 07103739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Method and apparatus for providing hardware aware logical volume mirrors' [patent_app_type] => utility [patent_app_number] => 10/682411 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6789 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103739.pdf [firstpage_image] =>[orig_patent_app_number] => 10682411 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682411
Method and apparatus for providing hardware aware logical volume mirrors Oct 8, 2003 Issued
Array ( [id] => 7245430 [patent_doc_number] => 20050080996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Increasing memory locality of filesystem synchronization operations' [patent_app_type] => utility [patent_app_number] => 10/682409 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2650 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20050080996.pdf [firstpage_image] =>[orig_patent_app_number] => 10682409 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682409
Increasing memory locality of filesystem synchronization operations Oct 8, 2003 Issued
Array ( [id] => 7245442 [patent_doc_number] => 20050080998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Method and apparatus for coherent memory structure of heterogeneous processor systems' [patent_app_type] => utility [patent_app_number] => 10/682386 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2555 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20050080998.pdf [firstpage_image] =>[orig_patent_app_number] => 10682386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682386
Method and apparatus for coherent memory structure of heterogeneous processor systems Oct 8, 2003 Issued
Array ( [id] => 7675922 [patent_doc_number] => 20040153905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Spare area management method of optical recording medium' [patent_app_type] => new [patent_app_number] => 10/679300 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5141 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153905.pdf [firstpage_image] =>[orig_patent_app_number] => 10679300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/679300
Spare area management method of optical recording medium Oct 6, 2003 Issued
Array ( [id] => 690657 [patent_doc_number] => 07080201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Disk array apparatus and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 10/659398 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9267 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080201.pdf [firstpage_image] =>[orig_patent_app_number] => 10659398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/659398
Disk array apparatus and method for controlling the same Sep 10, 2003 Issued
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