
Ramsey Refai
Examiner (ID: 1716, Phone: (313)446-4867 , Office: P/3687 )
| Most Active Art Unit | 3661 |
| Art Unit(s) | 3627, 2141, 3687, 3664, 2152, 3661, 3668, 2154 |
| Total Applications | 994 |
| Issued Applications | 512 |
| Pending Applications | 82 |
| Abandoned Applications | 415 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20532315
[patent_doc_number] => 12550769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-10
[patent_title] => Method for forming a package structure
[patent_app_type] => utility
[patent_app_number] => 18/602185
[patent_app_country] => US
[patent_app_date] => 2024-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602185
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/602185 | Method for forming a package structure | Mar 11, 2024 | Issued |
Array
(
[id] => 19399745
[patent_doc_number] => 12074133
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-08-27
[patent_title] => Chip bonding apparatus and securing assembly therefor
[patent_app_type] => utility
[patent_app_number] => 18/597172
[patent_app_country] => US
[patent_app_date] => 2024-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6489
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597172
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/597172 | Chip bonding apparatus and securing assembly therefor | Mar 5, 2024 | Issued |
Array
(
[id] => 19269467
[patent_doc_number] => 20240213171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY
[patent_app_type] => utility
[patent_app_number] => 18/596488
[patent_app_country] => US
[patent_app_date] => 2024-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7703
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596488
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/596488 | Ultra small molded module integrated with die by module-on-wafer assembly | Mar 4, 2024 | Issued |
Array
(
[id] => 19705097
[patent_doc_number] => 12199145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Epitaxial structure and transistor including the same
[patent_app_type] => utility
[patent_app_number] => 18/591803
[patent_app_country] => US
[patent_app_date] => 2024-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3545
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591803
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/591803 | Epitaxial structure and transistor including the same | Feb 28, 2024 | Issued |
Array
(
[id] => 19237442
[patent_doc_number] => 20240194637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => WAFER BONDING APPARATUS AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/582381
[patent_app_country] => US
[patent_app_date] => 2024-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13581
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582381
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/582381 | Wafer bonding apparatus and method | Feb 19, 2024 | Issued |
Array
(
[id] => 20153379
[patent_doc_number] => 20250253217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-07
[patent_title] => PACKAGE COMPRISING SUBSTRATES WITH POST INTERCONNECTS
[patent_app_type] => utility
[patent_app_number] => 18/430395
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7676
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430395
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/430395 | PACKAGE COMPRISING SUBSTRATES WITH POST INTERCONNECTS | Jan 31, 2024 | Pending |
Array
(
[id] => 20153384
[patent_doc_number] => 20250253222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-07
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/430507
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4198
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430507
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/430507 | SEMICONDUCTOR DEVICE | Jan 31, 2024 | Pending |
Array
(
[id] => 19893376
[patent_doc_number] => 20250118688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => CHIP PACKAGING STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/430600
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3883
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430600
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/430600 | CHIP PACKAGING STRUCTURE | Jan 31, 2024 | Pending |
Array
(
[id] => 20036387
[patent_doc_number] => 20250174609
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/430505
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430505
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/430505 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | Jan 31, 2024 | Pending |
Array
(
[id] => 19428190
[patent_doc_number] => 12087623
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-09-10
[patent_title] => Dielectric liners on through glass vias
[patent_app_type] => utility
[patent_app_number] => 18/422346
[patent_app_country] => US
[patent_app_date] => 2024-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 8008
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422346
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/422346 | Dielectric liners on through glass vias | Jan 24, 2024 | Issued |
Array
(
[id] => 19176176
[patent_doc_number] => 20240162150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/422017
[patent_app_country] => US
[patent_app_date] => 2024-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6594
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422017
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/422017 | Method of manufacturing semiconductor device | Jan 24, 2024 | Issued |
Array
(
[id] => 19174003
[patent_doc_number] => 20240159977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => SURFACE MOUNTABLE OPTOELECTRONIC DEVICE WITH SIDE WALLS INCLUDING SLOTS FILLED WITH A LAMINATED ENCAPSULANT MATERIAL
[patent_app_type] => utility
[patent_app_number] => 18/421768
[patent_app_country] => US
[patent_app_date] => 2024-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5277
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421768
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/421768 | SURFACE MOUNTABLE OPTOELECTRONIC DEVICE WITH SIDE WALLS INCLUDING SLOTS FILLED WITH A LAMINATED ENCAPSULANT MATERIAL | Jan 23, 2024 | Pending |
Array
(
[id] => 20760257
[patent_doc_number] => 12653052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-09
[patent_title] => Electronic package, package substrate and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/414740
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 1084
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 342
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414740
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/414740 | Electronic package, package substrate and manufacturing method thereof | Jan 16, 2024 | Issued |
Array
(
[id] => 19835769
[patent_doc_number] => 20250087555
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-13
[patent_title] => DIE STRUCTURES AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/404431
[patent_app_country] => US
[patent_app_date] => 2024-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10229
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404431
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/404431 | DIE STRUCTURES AND METHODS OF FORMING THE SAME | Jan 3, 2024 | Pending |
Array
(
[id] => 19704964
[patent_doc_number] => 12199011
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Embedded liquid cooling
[patent_app_type] => utility
[patent_app_number] => 18/399127
[patent_app_country] => US
[patent_app_date] => 2023-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 7891
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399127
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/399127 | Embedded liquid cooling | Dec 27, 2023 | Issued |
Array
(
[id] => 19670888
[patent_doc_number] => 12183659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-31
[patent_title] => Embedded cooling assemblies for advanced device packaging and methods of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/397505
[patent_app_country] => US
[patent_app_date] => 2023-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8648
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397505
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/397505 | Embedded cooling assemblies for advanced device packaging and methods of manufacturing the same | Dec 26, 2023 | Issued |
Array
(
[id] => 19128587
[patent_doc_number] => 20240133940
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-25
[patent_title] => MICRO DEVICE ARRANGEMENT IN DONOR SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/398124
[patent_app_country] => US
[patent_app_date] => 2023-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13214
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18398124
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/398124 | Micro device arrangement in donor substrate | Dec 26, 2023 | Issued |
Array
(
[id] => 19071225
[patent_doc_number] => 20240105651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => PACKAGE FOR POWER ELECTRONICS
[patent_app_type] => utility
[patent_app_number] => 18/530496
[patent_app_country] => US
[patent_app_date] => 2023-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5130
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530496
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/530496 | Package for power electronics | Dec 5, 2023 | Issued |
Array
(
[id] => 20720212
[patent_doc_number] => 12635484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-19
[patent_title] => Metal oxide layered structure and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/523457
[patent_app_country] => US
[patent_app_date] => 2023-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 32
[patent_no_of_words] => 4839
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523457
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/523457 | Metal oxide layered structure and methods of forming the same | Nov 28, 2023 | Issued |
Array
(
[id] => 19951371
[patent_doc_number] => 12322742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Semiconductor structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/518636
[patent_app_country] => US
[patent_app_date] => 2023-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 28
[patent_no_of_words] => 6104
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518636
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/518636 | Semiconductor structure and manufacturing method thereof | Nov 23, 2023 | Issued |