Search

Ramsey Refai

Examiner (ID: 1716, Phone: (313)446-4867 , Office: P/3687 )

Most Active Art Unit
3661
Art Unit(s)
3627, 2141, 3687, 3664, 2152, 3661, 3668, 2154
Total Applications
994
Issued Applications
512
Pending Applications
82
Abandoned Applications
415

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16835228 [patent_doc_number] => 11011488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Zinc-cobalt barrier for interface in solder bond applications [patent_app_type] => utility [patent_app_number] => 16/660187 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 5844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660187
Zinc-cobalt barrier for interface in solder bond applications Oct 21, 2019 Issued
Array ( [id] => 17381243 [patent_doc_number] => 11239276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => CMOS color image sensors with metamaterial color splitting [patent_app_type] => utility [patent_app_number] => 16/657640 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 4894 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657640
CMOS color image sensors with metamaterial color splitting Oct 17, 2019 Issued
Array ( [id] => 15503681 [patent_doc_number] => 20200052029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => ELECTRIC MODULE, ENDOSCOPE, AND METHOD FOR MANUFACTURING ELECTRIC MODULE [patent_app_type] => utility [patent_app_number] => 16/657522 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657522 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657522
ELECTRIC MODULE, ENDOSCOPE, AND METHOD FOR MANUFACTURING ELECTRIC MODULE Oct 17, 2019 Abandoned
Array ( [id] => 19138120 [patent_doc_number] => 11973096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Solid-state imaging element, solid-state imaging element package, and electronic equipment [patent_app_type] => utility [patent_app_number] => 17/285691 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12138 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17285691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/285691
Solid-state imaging element, solid-state imaging element package, and electronic equipment Oct 10, 2019 Issued
Array ( [id] => 18429970 [patent_doc_number] => 11675186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Hermetically sealed MEMS mirror and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/591854 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 2649 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591854
Hermetically sealed MEMS mirror and method of manufacture Oct 2, 2019 Issued
Array ( [id] => 16944216 [patent_doc_number] => 11056467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Semiconductor devices with through silicon vias and package-level configurability [patent_app_type] => utility [patent_app_number] => 16/590595 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6008 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590595 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/590595
Semiconductor devices with through silicon vias and package-level configurability Oct 1, 2019 Issued
Array ( [id] => 16635510 [patent_doc_number] => 10914008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Method and solution for forming interconnects [patent_app_type] => utility [patent_app_number] => 16/586483 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 9915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586483
Method and solution for forming interconnects Sep 26, 2019 Issued
Array ( [id] => 17303301 [patent_doc_number] => 20210399140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/279153 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17279153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/279153
Semiconductor device Sep 26, 2019 Issued
16/586252 INTEGRATED CIRCUIT (IC) PACKAGE WITH CANTILEVER MULTI-CHIP MODULE (MCM) HEAT SPREADER Sep 26, 2019 Abandoned
Array ( [id] => 16731292 [patent_doc_number] => 20210098440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => PACKAGED DEVICE WITH A CHIPLET COMPRISING MEMORY RESOURCES [patent_app_type] => utility [patent_app_number] => 16/586167 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586167
Packaged device with a chiplet comprising memory resources Sep 26, 2019 Issued
Array ( [id] => 16624946 [patent_doc_number] => 20210043599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Cu ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/976069 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16976069 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/976069
Cu alloy bonding wire for semiconductor device Sep 19, 2019 Issued
Array ( [id] => 17332384 [patent_doc_number] => 11222852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Method for fabricating electronic package [patent_app_type] => utility [patent_app_number] => 16/573276 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3838 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573276
Method for fabricating electronic package Sep 16, 2019 Issued
Array ( [id] => 15717661 [patent_doc_number] => 20200105598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => Structure and Method for Interconnection with Self-Alignment [patent_app_type] => utility [patent_app_number] => 16/560717 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560717 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560717
Structure and method for interconnection with self-alignment Sep 3, 2019 Issued
Array ( [id] => 16471702 [patent_doc_number] => 20200373240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => DESIGN APPLICATIONS OF BURIED POWER RAILS [patent_app_type] => utility [patent_app_number] => 16/561006 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561006
Applications of buried power rails Sep 3, 2019 Issued
Array ( [id] => 15598073 [patent_doc_number] => 20200075571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/560870 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560870
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME Sep 3, 2019 Abandoned
Array ( [id] => 16566875 [patent_doc_number] => 10892251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/559409 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3728 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559409 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559409
Semiconductor device Sep 2, 2019 Issued
Array ( [id] => 16677473 [patent_doc_number] => 20210066239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => PACKAGED SEMICONDUCTOR DEVICES WITH UNIFORM SOLDER JOINTS [patent_app_type] => utility [patent_app_number] => 16/559410 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559410
PACKAGED SEMICONDUCTOR DEVICES WITH UNIFORM SOLDER JOINTS Sep 2, 2019 Abandoned
Array ( [id] => 16789179 [patent_doc_number] => 10991618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/559450 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559450
Semiconductor device and method of manufacture Sep 2, 2019 Issued
Array ( [id] => 16699954 [patent_doc_number] => 10950562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => Impedance-matched through-wafer transition using integrated heat-spreader technology [patent_app_type] => utility [patent_app_number] => 16/559486 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559486
Impedance-matched through-wafer transition using integrated heat-spreader technology Sep 2, 2019 Issued
Array ( [id] => 16707639 [patent_doc_number] => 10957583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs [patent_app_type] => utility [patent_app_number] => 16/553342 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553342 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553342
Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs Aug 27, 2019 Issued
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