Search

Ramsey Refai

Examiner (ID: 1716, Phone: (313)446-4867 , Office: P/3687 )

Most Active Art Unit
3661
Art Unit(s)
3627, 2141, 3687, 3664, 2152, 3661, 3668, 2154
Total Applications
994
Issued Applications
512
Pending Applications
82
Abandoned Applications
415

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14475641 [patent_doc_number] => 20190189468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 16/220125 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220125
Semiconductor device and method of manufacture Dec 13, 2018 Issued
Array ( [id] => 15250245 [patent_doc_number] => 10510651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro [patent_app_type] => utility [patent_app_number] => 16/220764 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4002 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220764
Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro Dec 13, 2018 Issued
Array ( [id] => 16218730 [patent_doc_number] => 10734553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor light emitting device with light extraction structures [patent_app_type] => utility [patent_app_number] => 16/220864 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220864
Semiconductor light emitting device with light extraction structures Dec 13, 2018 Issued
Array ( [id] => 18766951 [patent_doc_number] => 11817360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Chip scale package semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/220160 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3325 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220160
Chip scale package semiconductor device and method of manufacture Dec 13, 2018 Issued
Array ( [id] => 14238183 [patent_doc_number] => 20190131264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => Semiconductor Device Structure and Manufacturing Method [patent_app_type] => utility [patent_app_number] => 16/219453 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219453
Semiconductor device structure and manufacturing method Dec 12, 2018 Issued
Array ( [id] => 14163929 [patent_doc_number] => 20190109067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/216044 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216044 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216044
Semiconductor chip and semiconductor device Dec 10, 2018 Issued
Array ( [id] => 14191187 [patent_doc_number] => 20190115299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => Conductive Vias in Semiconductor Packages and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 16/206850 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/206850
Conductive vias in semiconductor packages and methods of forming same Nov 29, 2018 Issued
Array ( [id] => 14110363 [patent_doc_number] => 20190096857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 16/203555 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203555
Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices Nov 27, 2018 Issued
Array ( [id] => 14110371 [patent_doc_number] => 20190096861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => MICROELECTRONIC PACKAGE FOR WAFER-LEVEL CHIP SCALE PACKAGING WITH FAN-OUT [patent_app_type] => utility [patent_app_number] => 16/201569 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201569 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201569
MICROELECTRONIC PACKAGE FOR WAFER-LEVEL CHIP SCALE PACKAGING WITH FAN-OUT Nov 26, 2018 Abandoned
Array ( [id] => 16386510 [patent_doc_number] => 10811355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Methods of forming semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/200902 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 8161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200902 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200902
Methods of forming semiconductor devices Nov 26, 2018 Issued
Array ( [id] => 16803296 [patent_doc_number] => 10998249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Semiconductor assembly [patent_app_type] => utility [patent_app_number] => 16/958067 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6526 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16958067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/958067
Semiconductor assembly Nov 18, 2018 Issued
Array ( [id] => 17055866 [patent_doc_number] => 20210265300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => BONDING SYSTEM AND BONDING METHOD [patent_app_type] => utility [patent_app_number] => 17/269513 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17269513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/269513
BONDING SYSTEM AND BONDING METHOD Nov 13, 2018 Pending
Array ( [id] => 16456205 [patent_doc_number] => 20200365631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => IMPROVED HYBRID OPTICAL/ELECTRONIC SYSTEM [patent_app_type] => utility [patent_app_number] => 16/763549 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16763549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/763549
Hybrid optical/electronic system Nov 12, 2018 Issued
Array ( [id] => 18371933 [patent_doc_number] => 11652115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Solid-state imaging device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/758537 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 81 [patent_no_of_words] => 36930 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16758537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/758537
Solid-state imaging device and electronic apparatus Nov 8, 2018 Issued
Array ( [id] => 15873347 [patent_doc_number] => 20200144077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => METHOD OF APPLYING CONDUCTIVE ADHESIVE AND MANUFACTURING DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/183435 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183435 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183435
Method of applying conductive adhesive and manufacturing device using the same Nov 6, 2018 Issued
Array ( [id] => 13995899 [patent_doc_number] => 20190067107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => METHOD OF MAKING A SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS [patent_app_type] => utility [patent_app_number] => 16/168306 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168306
Method of making a semiconductor component having through-silicon vias Oct 22, 2018 Issued
Array ( [id] => 13936145 [patent_doc_number] => 20190051588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE PROVIDED WITH SAME [patent_app_type] => utility [patent_app_number] => 16/165486 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165486
Semiconductor chip and semiconductor device provided with same Oct 18, 2018 Issued
Array ( [id] => 16988075 [patent_doc_number] => 11075258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Display substrate, manufacturing method thereof, corresponding display panel and encapsulation method for the same [patent_app_type] => utility [patent_app_number] => 16/346355 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16346355 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/346355
Display substrate, manufacturing method thereof, corresponding display panel and encapsulation method for the same Oct 17, 2018 Issued
Array ( [id] => 13936231 [patent_doc_number] => 20190051631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING ONE OR MORE WINDOWS AND RELATED METHODS AND PACKAGES [patent_app_type] => utility [patent_app_number] => 16/162070 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/162070
Package-on-package semiconductor device assemblies including one or more windows and related methods and packages Oct 15, 2018 Issued
Array ( [id] => 16324214 [patent_doc_number] => 10784186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Semiconductor module [patent_app_type] => utility [patent_app_number] => 16/162082 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7975 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/162082
Semiconductor module Oct 15, 2018 Issued
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