
Ramsey Refai
Examiner (ID: 1716, Phone: (313)446-4867 , Office: P/3687 )
| Most Active Art Unit | 3661 |
| Art Unit(s) | 3627, 2141, 3687, 3664, 2152, 3661, 3668, 2154 |
| Total Applications | 994 |
| Issued Applications | 512 |
| Pending Applications | 82 |
| Abandoned Applications | 415 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20566183
[patent_doc_number] => 12568810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-03
[patent_title] => Anti-diffusion substrate structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/088204
[patent_app_country] => US
[patent_app_date] => 2022-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 0
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088204
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/088204 | Anti-diffusion substrate structure and manufacturing method thereof | Dec 22, 2022 | Issued |
Array
(
[id] => 18323013
[patent_doc_number] => 20230121141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => SEMICONDUCTOR PACKAGES WITH INDICATIONS OF DIE-SPECIFIC INFORMATION
[patent_app_type] => utility
[patent_app_number] => 18/083963
[patent_app_country] => US
[patent_app_date] => 2022-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083963
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/083963 | SEMICONDUCTOR PACKAGES WITH INDICATIONS OF DIE-SPECIFIC INFORMATION | Dec 18, 2022 | Abandoned |
Array
(
[id] => 19727187
[patent_doc_number] => 20250029938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => FUNCTIONAL SUBSTRATE AND METHOD FOR MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 18/280978
[patent_app_country] => US
[patent_app_date] => 2022-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11064
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18280978
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/280978 | FUNCTIONAL SUBSTRATE AND METHOD FOR MANUFACTURING SAME | Dec 15, 2022 | Pending |
Array
(
[id] => 19016359
[patent_doc_number] => 11923301
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-05
[patent_title] => Method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/066292
[patent_app_country] => US
[patent_app_date] => 2022-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6664
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066292
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/066292 | Method of manufacturing semiconductor device | Dec 14, 2022 | Issued |
Array
(
[id] => 18586105
[patent_doc_number] => 20230268370
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => IMAGE SENSOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/063268
[patent_app_country] => US
[patent_app_date] => 2022-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15051
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063268
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/063268 | Image sensor package | Dec 7, 2022 | Issued |
Array
(
[id] => 19221547
[patent_doc_number] => 20240186251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => SYMMETRIC DUMMY BRIDGE DESIGN FOR FLI ALIGNMENT IMPROVEMENT
[patent_app_type] => utility
[patent_app_number] => 18/075360
[patent_app_country] => US
[patent_app_date] => 2022-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6408
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075360
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/075360 | SYMMETRIC DUMMY BRIDGE DESIGN FOR FLI ALIGNMENT IMPROVEMENT | Dec 4, 2022 | Pending |
Array
(
[id] => 20375278
[patent_doc_number] => 12482722
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => Disc cell assembly clamp
[patent_app_type] => utility
[patent_app_number] => 18/071845
[patent_app_country] => US
[patent_app_date] => 2022-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 0
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071845
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/071845 | Disc cell assembly clamp | Nov 29, 2022 | Issued |
Array
(
[id] => 19500557
[patent_doc_number] => 20240339575
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => LIGHT EMITTING DIODE CHIP AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/293834
[patent_app_country] => US
[patent_app_date] => 2022-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11144
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18293834
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/293834 | LIGHT EMITTING DIODE CHIP AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE | Nov 29, 2022 | Pending |
Array
(
[id] => 18983552
[patent_doc_number] => 11908740
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Semiconductor structure with doped via plug
[patent_app_type] => utility
[patent_app_number] => 17/994153
[patent_app_country] => US
[patent_app_date] => 2022-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8609
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994153
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/994153 | Semiconductor structure with doped via plug | Nov 24, 2022 | Issued |
Array
(
[id] => 19191438
[patent_doc_number] => 20240170351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => REDISTRIBUTION LAYERS IN A DIELECTRIC CAVITY TO ENABLE AN EMBEDDED COMPONENT
[patent_app_type] => utility
[patent_app_number] => 17/992010
[patent_app_country] => US
[patent_app_date] => 2022-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12165
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992010
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/992010 | REDISTRIBUTION LAYERS IN A DIELECTRIC CAVITY TO ENABLE AN EMBEDDED COMPONENT | Nov 21, 2022 | Pending |
Array
(
[id] => 19191481
[patent_doc_number] => 20240170394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => INTEGRATED CIRCUIT INTERCONNECT LEVEL COMPRISING MULTI-HEIGHT LINES & SELF-ALIGNED VIAS
[patent_app_type] => utility
[patent_app_number] => 17/992818
[patent_app_country] => US
[patent_app_date] => 2022-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992818
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/992818 | INTEGRATED CIRCUIT INTERCONNECT LEVEL COMPRISING MULTI-HEIGHT LINES & SELF-ALIGNED VIAS | Nov 21, 2022 | Pending |
Array
(
[id] => 19191486
[patent_doc_number] => 20240170399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => SEMICONDUCTOR DEVICE WITH LINES AND VIAS WITH VARIABLE HEIGHT FOR LOCAL RC OPTIMIZATION
[patent_app_type] => utility
[patent_app_number] => 18/057884
[patent_app_country] => US
[patent_app_date] => 2022-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10335
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057884
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/057884 | SEMICONDUCTOR DEVICE WITH LINES AND VIAS WITH VARIABLE HEIGHT FOR LOCAL RC OPTIMIZATION | Nov 21, 2022 | Pending |
Array
(
[id] => 19951358
[patent_doc_number] => 12322729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/057222
[patent_app_country] => US
[patent_app_date] => 2022-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 1089
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 358
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057222
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/057222 | Semiconductor device | Nov 19, 2022 | Issued |
Array
(
[id] => 18256373
[patent_doc_number] => 20230083412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/989894
[patent_app_country] => US
[patent_app_date] => 2022-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9750
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989894
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/989894 | Semiconductor package having routable encapsulated conductive substrate and method | Nov 17, 2022 | Issued |
Array
(
[id] => 19191375
[patent_doc_number] => 20240170288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => INFRARED DEBOND DAMAGE MITIGATION BY COPPER FILL PATTERN
[patent_app_type] => utility
[patent_app_number] => 18/056393
[patent_app_country] => US
[patent_app_date] => 2022-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4563
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056393
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/056393 | Infrared debond damage mitigation by copper fill pattern | Nov 16, 2022 | Issued |
Array
(
[id] => 19176183
[patent_doc_number] => 20240162157
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => BUMPLESS HYBRID ORGANIC GLASS INTERPOSER
[patent_app_type] => utility
[patent_app_number] => 17/988051
[patent_app_country] => US
[patent_app_date] => 2022-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988051
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/988051 | BUMPLESS HYBRID ORGANIC GLASS INTERPOSER | Nov 15, 2022 | Pending |
Array
(
[id] => 19176218
[patent_doc_number] => 20240162192
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => STACKED 3D CACHE CONFIGURATION WITH ON-CHIP POWER SUPPORT
[patent_app_type] => utility
[patent_app_number] => 17/987823
[patent_app_country] => US
[patent_app_date] => 2022-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4371
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987823
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/987823 | STACKED 3D CACHE CONFIGURATION WITH ON-CHIP POWER SUPPORT | Nov 14, 2022 | Pending |
Array
(
[id] => 19176226
[patent_doc_number] => 20240162200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => LAMINATION OF A LIGHT SOURCE HAVING A LOW-DENSITY SET OF LIGHT-EMITTING ELEMENTS
[patent_app_type] => utility
[patent_app_number] => 17/985894
[patent_app_country] => US
[patent_app_date] => 2022-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11605
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985894
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/985894 | LAMINATION OF A LIGHT SOURCE HAVING A LOW-DENSITY SET OF LIGHT-EMITTING ELEMENTS | Nov 12, 2022 | Pending |
Array
(
[id] => 19183837
[patent_doc_number] => 11990438
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-21
[patent_title] => Chiplets with connection posts
[patent_app_type] => utility
[patent_app_number] => 17/984748
[patent_app_country] => US
[patent_app_date] => 2022-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 32
[patent_no_of_words] => 13797
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984748
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/984748 | Chiplets with connection posts | Nov 9, 2022 | Issued |
Array
(
[id] => 19161101
[patent_doc_number] => 20240153808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => CHIP CHUCK AND A METHOD OF USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/053410
[patent_app_country] => US
[patent_app_date] => 2022-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12217
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053410
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/053410 | Chip chuck and a method of using the same | Nov 7, 2022 | Issued |