Search

Randall H. Gholson

Examiner (ID: 7575, Phone: (571)272-1011 , Office: P/2918 )

Most Active Art Unit
2918
Art Unit(s)
2918, 2915
Total Applications
3041
Issued Applications
3007
Pending Applications
0
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11966810 [patent_doc_number] => 20170270963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'MAGNETIC DISK DEVICE, DATA PROCESSING DEVICE AND RECORDING METHOD' [patent_app_type] => utility [patent_app_number] => 15/252612 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252612
MAGNETIC DISK DEVICE, DATA PROCESSING DEVICE AND RECORDING METHOD Aug 30, 2016 Abandoned
Array ( [id] => 12224310 [patent_doc_number] => 20180062671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEQUENCE DETECTORS' [patent_app_type] => utility [patent_app_number] => 15/251638 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15251638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/251638
Sequence detectors Aug 29, 2016 Issued
Array ( [id] => 13948293 [patent_doc_number] => 10209921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Expanding slice count in response to low-level failures [patent_app_type] => utility [patent_app_number] => 15/249353 [patent_app_country] => US [patent_app_date] => 2016-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6722 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15249353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/249353
Expanding slice count in response to low-level failures Aug 26, 2016 Issued
Array ( [id] => 13212455 [patent_doc_number] => 10120596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Adaptive extra write issuance within a dispersed storage network (DSN) [patent_app_type] => utility [patent_app_number] => 15/249084 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15249084 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/249084
Adaptive extra write issuance within a dispersed storage network (DSN) Aug 25, 2016 Issued
Array ( [id] => 13240851 [patent_doc_number] => 10133624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Fault localization and error correction method for self-checking binary signed-digit adder and digital logic circuit for the method [patent_app_type] => utility [patent_app_number] => 15/247185 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4353 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247185 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/247185
Fault localization and error correction method for self-checking binary signed-digit adder and digital logic circuit for the method Aug 24, 2016 Issued
Array ( [id] => 11825477 [patent_doc_number] => 20170214415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'MEMORY SYSTEM USING INTEGRATED PARALLEL INTERLEAVED CONCATENATION' [patent_app_type] => utility [patent_app_number] => 15/244412 [patent_app_country] => US [patent_app_date] => 2016-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10582 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15244412 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/244412
Memory system using integrated parallel interleaved concatenation Aug 22, 2016 Issued
Array ( [id] => 11606603 [patent_doc_number] => 20170123907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'END-TO-END SECURE DATA STORAGE IN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 15/238106 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6725 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238106
End-to-end secure data storage in a dispersed storage network Aug 15, 2016 Issued
Array ( [id] => 11531053 [patent_doc_number] => 20170091031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'END-TO-END SECURE DATA RETRIEVAL IN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 15/237874 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6762 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15237874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/237874
End-to-end secure data retrieval in a dispersed storage network Aug 15, 2016 Issued
Array ( [id] => 11316255 [patent_doc_number] => 20160352364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'MAX-LOG-MAP EQUIVALENCE LOG LIKELIHOOD RATIO GENERATION SOFT VITERBI ARCHITECTURE SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/234122 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 11274 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234122 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234122
MAX-LOG-MAP EQUIVALENCE LOG LIKELIHOOD RATIO GENERATION SOFT VITERBI ARCHITECTURE SYSTEM AND METHOD Aug 10, 2016 Abandoned
Array ( [id] => 11126012 [patent_doc_number] => 20160322988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'DTV TRANSMITTING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA' [patent_app_type] => utility [patent_app_number] => 15/208161 [patent_app_country] => US [patent_app_date] => 2016-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 27821 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/208161
DTV transmitting system and method of processing broadcast data Jul 11, 2016 Issued
Array ( [id] => 12123179 [patent_doc_number] => 20180006765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'Method and Encoding Device for Encoding a Sequence of M-Bit Pattern Words and Outputting a Frame Comprising Corresponding N-Bit Symbols' [patent_app_type] => utility [patent_app_number] => 15/196711 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10125 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196711 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/196711
Method and encoding device for encoding a sequence of m-bit pattern words and outputting a frame comprising corresponding n-bit symbols Jun 28, 2016 Issued
Array ( [id] => 12121010 [patent_doc_number] => 20180004596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'ERROR CORRECTION CODE EVENT DETECTION' [patent_app_type] => utility [patent_app_number] => 15/197446 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13305 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197446 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/197446
Error correction code event detection Jun 28, 2016 Issued
Array ( [id] => 14986805 [patent_doc_number] => 10447328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Systems and methods for die-to-die communication [patent_app_type] => utility [patent_app_number] => 15/194776 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6671 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194776 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194776
Systems and methods for die-to-die communication Jun 27, 2016 Issued
Array ( [id] => 16280951 [patent_doc_number] => 10763998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Enhanced feedback signalling [patent_app_type] => utility [patent_app_number] => 16/313517 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10310 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16313517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/313517
Enhanced feedback signalling Jun 27, 2016 Issued
Array ( [id] => 13721573 [patent_doc_number] => 20170371741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => TECHNOLOGIES FOR PROVIDING FILE-BASED RESILIENCY [patent_app_type] => utility [patent_app_number] => 15/193337 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193337
TECHNOLOGIES FOR PROVIDING FILE-BASED RESILIENCY Jun 26, 2016 Abandoned
Array ( [id] => 14123281 [patent_doc_number] => 10248499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Non-volatile storage system using two pass programming with bit error control [patent_app_type] => utility [patent_app_number] => 15/192901 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 14311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192901 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192901
Non-volatile storage system using two pass programming with bit error control Jun 23, 2016 Issued
Array ( [id] => 13721577 [patent_doc_number] => 20170371743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SYSTEM AND METHOD FOR PROTECTING GPU MEMORY INSTRUCTIONS AGAINST FAULTS [patent_app_type] => utility [patent_app_number] => 15/190015 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15190015 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/190015
System and method for protecting GPU memory instructions against faults Jun 21, 2016 Issued
Array ( [id] => 11366061 [patent_doc_number] => 20170004042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'ACCELERATING SLICE TRANSFERS UTILIZING MULTIPLE INTERFACES' [patent_app_type] => utility [patent_app_number] => 15/187923 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15187923 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/187923
Accelerating slice transfers utilizing multiple interfaces Jun 20, 2016 Issued
Array ( [id] => 13272653 [patent_doc_number] => 10148417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Duty-cycled high speed clock and data recovery with forward error correction assist [patent_app_type] => utility [patent_app_number] => 15/185429 [patent_app_country] => US [patent_app_date] => 2016-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15185429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/185429
Duty-cycled high speed clock and data recovery with forward error correction assist Jun 16, 2016 Issued
Array ( [id] => 12495381 [patent_doc_number] => 09996412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Enhanced chip-kill schemes by using sub-trunk CRC [patent_app_type] => utility [patent_app_number] => 15/184845 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4405 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184845 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184845
Enhanced chip-kill schemes by using sub-trunk CRC Jun 15, 2016 Issued
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