Search

Randall H. Gholson

Examiner (ID: 7575, Phone: (571)272-1011 , Office: P/2918 )

Most Active Art Unit
2918
Art Unit(s)
2918, 2915
Total Applications
3041
Issued Applications
3007
Pending Applications
0
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18486947 [patent_doc_number] => 20230214293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => DETECT MULTIFOLD DISTURBANCE AND MINIMIZE READ-DISTURB ERRORS IN NAND FLASH [patent_app_type] => utility [patent_app_number] => 17/568830 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568830
Detect multifold disturbance and minimize read-disturb errors in NAND flash Jan 4, 2022 Issued
Array ( [id] => 18474160 [patent_doc_number] => 20230208448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => Variable Length ECC Code According to Value Length in NVMe Key Value Pair Devices [patent_app_type] => utility [patent_app_number] => 17/562105 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562105 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562105
Variable length ECC code according to value length in NVMe key value pair devices Dec 26, 2021 Issued
Array ( [id] => 18638130 [patent_doc_number] => 11762732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Memory error detection and correction [patent_app_type] => utility [patent_app_number] => 17/556101 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556101
Memory error detection and correction Dec 19, 2021 Issued
Array ( [id] => 17675020 [patent_doc_number] => 20220188187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ERROR CORRECTING MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/554505 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554505
Error correcting memory systems Dec 16, 2021 Issued
Array ( [id] => 18703302 [patent_doc_number] => 11789813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Memory device crossed matrix parity [patent_app_type] => utility [patent_app_number] => 17/553041 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/553041
Memory device crossed matrix parity Dec 15, 2021 Issued
Array ( [id] => 18438367 [patent_doc_number] => 20230185662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => MEMORY ARRAY ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/548057 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548057
Memory array error correction Dec 9, 2021 Issued
Array ( [id] => 18400768 [patent_doc_number] => 11662904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning [patent_app_type] => utility [patent_app_number] => 17/545926 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12118 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545926
Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning Dec 7, 2021 Issued
Array ( [id] => 18087333 [patent_doc_number] => 11537468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Recording memory errors for use after restarts [patent_app_type] => utility [patent_app_number] => 17/457679 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457679
Recording memory errors for use after restarts Dec 5, 2021 Issued
Array ( [id] => 18248104 [patent_doc_number] => 11604692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Field programmable gate array (FPGA) with automatic error detection and correction function for programmable logic modules [patent_app_type] => utility [patent_app_number] => 17/457440 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4291 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457440
Field programmable gate array (FPGA) with automatic error detection and correction function for programmable logic modules Dec 2, 2021 Issued
Array ( [id] => 17947902 [patent_doc_number] => 20220334921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE AND HOST DEVICE [patent_app_type] => utility [patent_app_number] => 17/539898 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539898
Memory device and operating method of the memory device and host device Nov 30, 2021 Issued
Array ( [id] => 17484423 [patent_doc_number] => 20220091927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD AND APPARATUS TO REDUCE BANDWIDTH OVERHEAD OF CRC PROTECTION ON A MEMORY CHANNEL [patent_app_type] => utility [patent_app_number] => 17/539813 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539813
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel Nov 30, 2021 Issued
Array ( [id] => 18079555 [patent_doc_number] => 20220405167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR MEMORY APPARATUS AND OPERATION METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS, AND MEMORY SYSTEM HAVING THE SEMICONDUCTOR MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/536814 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536814
Semiconductor memory apparatus and operation method of the semiconductor memory apparatus, and memory system having the semiconductor memory apparatus Nov 28, 2021 Issued
Array ( [id] => 18393446 [patent_doc_number] => 20230161666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => ECC PARITY BIASING FOR KEY-VALUE DATA STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 17/531975 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531975
ECC parity biasing for Key-Value data storage devices Nov 21, 2021 Issued
Array ( [id] => 19780600 [patent_doc_number] => 12229634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Stark shift cancellation [patent_app_type] => utility [patent_app_number] => 17/526852 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16744 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526852
Stark shift cancellation Nov 14, 2021 Issued
Array ( [id] => 17778675 [patent_doc_number] => 20220245025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => TECHNIQUES FOR DATA SCRAMBLING ON A MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 17/523775 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523775
Techniques for data scrambling on a memory interface Nov 9, 2021 Issued
Array ( [id] => 17430376 [patent_doc_number] => 20220058085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/519356 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519356
Memory system Nov 3, 2021 Issued
Array ( [id] => 18797494 [patent_doc_number] => 11831340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Burst error tolerant decoder and related systems, methods, and devices [patent_app_type] => utility [patent_app_number] => 17/453119 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10165 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453119
Burst error tolerant decoder and related systems, methods, and devices Oct 31, 2021 Issued
Array ( [id] => 18949988 [patent_doc_number] => 11893284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Method, device and system for testing memory devices [patent_app_type] => utility [patent_app_number] => 17/452857 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6316 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452857
Method, device and system for testing memory devices Oct 28, 2021 Issued
Array ( [id] => 18347578 [patent_doc_number] => 20230135688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => TECHNIQUES FOR ERROR CORRECTION AT A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/515033 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515033
Techniques for error correction at a memory device Oct 28, 2021 Issued
Array ( [id] => 18547090 [patent_doc_number] => 11720442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Memory controller performing selective and parallel error correction, system including the same and operating method of memory device [patent_app_type] => utility [patent_app_number] => 17/510898 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 10760 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510898
Memory controller performing selective and parallel error correction, system including the same and operating method of memory device Oct 25, 2021 Issued
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