Search

Randolph I. Chu

Examiner (ID: 12496, Phone: (571)270-1145 , Office: P/2666 )

Most Active Art Unit
2666
Art Unit(s)
2624, 2666, 2663, 2668, 2667
Total Applications
974
Issued Applications
744
Pending Applications
78
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17367280 [patent_doc_number] => 11234329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Prepreg, substrate, metal-clad laminate, semiconductor package, and printed circuit board [patent_app_type] => utility [patent_app_number] => 16/954020 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 41 [patent_no_of_words] => 19977 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16954020 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/954020
Prepreg, substrate, metal-clad laminate, semiconductor package, and printed circuit board Dec 3, 2018 Issued
Array ( [id] => 14707107 [patent_doc_number] => 10381313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Semiconductor device and method of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/197328 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197328 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197328
Semiconductor device and method of manufacturing a semiconductor device Nov 19, 2018 Issued
Array ( [id] => 15170033 [patent_doc_number] => 10490520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Multichip modules and methods of fabrication [patent_app_type] => utility [patent_app_number] => 16/196313 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 43 [patent_no_of_words] => 18810 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/196313
Multichip modules and methods of fabrication Nov 19, 2018 Issued
Array ( [id] => 14644369 [patent_doc_number] => 10366934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Face down dual sided chip scale memory package [patent_app_type] => utility [patent_app_number] => 16/196262 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6984 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/196262
Face down dual sided chip scale memory package Nov 19, 2018 Issued
Array ( [id] => 16035051 [patent_doc_number] => 10679958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Methods of manufacturing a multi-device package [patent_app_type] => utility [patent_app_number] => 16/195241 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16195241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/195241
Methods of manufacturing a multi-device package Nov 18, 2018 Issued
Array ( [id] => 14079429 [patent_doc_number] => 20190088602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/194553 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194553 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194553
Semiconductor device and method for manufacturing same Nov 18, 2018 Issued
Array ( [id] => 14079383 [patent_doc_number] => 20190088579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => METHODS OF FORMING LEADLESS SEMICONDUCTOR PACKAGES WITH PLATED LEADFRAMES AND WETTABLE FLANKS [patent_app_type] => utility [patent_app_number] => 16/194734 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194734 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194734
Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks Nov 18, 2018 Issued
Array ( [id] => 15807663 [patent_doc_number] => 20200126974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE HAVING SEMICONDUCTOR PLUG FORMED USING BACKSIDE SUBSTRATE THINNING [patent_app_type] => utility [patent_app_number] => 16/194309 [patent_app_country] => US [patent_app_date] => 2018-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194309
Three-dimensional memory device having semiconductor plug formed using backside substrate thinning Nov 16, 2018 Issued
Array ( [id] => 15673079 [patent_doc_number] => 10600781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-24 [patent_title] => Multi-stack three-dimensional memory devices [patent_app_type] => utility [patent_app_number] => 16/194263 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 12711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16194263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/194263
Multi-stack three-dimensional memory devices Nov 15, 2018 Issued
Array ( [id] => 14079415 [patent_doc_number] => 20190088595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Wireless Charging Package with Chip Integrated in Coil Center [patent_app_type] => utility [patent_app_number] => 16/192005 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192005
Wireless charging package with chip integrated in coil center Nov 14, 2018 Issued
Array ( [id] => 14350219 [patent_doc_number] => 20190157082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => METHOD AND STRUCTURE FOR CUTTING DENSE LINE PATTERNS USING SELF-ALIGNED DOUBLE PATTERNING [patent_app_type] => utility [patent_app_number] => 16/183174 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183174
Method and structure for cutting dense line patterns using self-aligned double patterning Nov 6, 2018 Issued
Array ( [id] => 16202115 [patent_doc_number] => 10727295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Wafer level package and capacitor [patent_app_type] => utility [patent_app_number] => 16/176506 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 8838 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176506 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176506
Wafer level package and capacitor Oct 30, 2018 Issued
Array ( [id] => 16301074 [patent_doc_number] => 20200286797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SYSTEM AND METHOD FOR ALLOWING RESTORATION OF FIRST INTERCONNECTION OF DIE OF POWER MODULE [patent_app_type] => utility [patent_app_number] => 16/755412 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16755412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/755412
System and method for allowing restoration of first interconnection of die of power module Oct 30, 2018 Issued
Array ( [id] => 17941715 [patent_doc_number] => 11476174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Solder mask design for delamination prevention [patent_app_type] => utility [patent_app_number] => 16/177046 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177046
Solder mask design for delamination prevention Oct 30, 2018 Issued
Array ( [id] => 16264611 [patent_doc_number] => 10756056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Methods and structures for wafer-level system in package [patent_app_type] => utility [patent_app_number] => 16/176098 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 12115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176098
Methods and structures for wafer-level system in package Oct 30, 2018 Issued
Array ( [id] => 16187060 [patent_doc_number] => 10720399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Semicondcutor package and manufacturing method of semicondcutor package [patent_app_type] => utility [patent_app_number] => 16/171335 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171335
Semicondcutor package and manufacturing method of semicondcutor package Oct 24, 2018 Issued
Array ( [id] => 16067545 [patent_doc_number] => 10692734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Methods of patterning nickel silicide layers on a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/171053 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171053
Methods of patterning nickel silicide layers on a semiconductor device Oct 24, 2018 Issued
Array ( [id] => 14691581 [patent_doc_number] => 20190244906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => SEMICONDUCTOR PACKAGES AND DISPLAY DEVICES INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/170804 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 1 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170804
Semiconductor packages and display devices including the same Oct 24, 2018 Issued
Array ( [id] => 15045751 [patent_doc_number] => 20190333880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => FAN-OUT ANTENNA PACKAGING STRUCTURE AND PREPARATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/171054 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171054 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171054
Fan-out antenna packaging structure and preparation method thereof Oct 24, 2018 Issued
Array ( [id] => 15580737 [patent_doc_number] => 10580762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Integrated circuit (IC) chip arrangement [patent_app_type] => utility [patent_app_number] => 16/170761 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170761 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170761
Integrated circuit (IC) chip arrangement Oct 24, 2018 Issued
Menu