Search

Randolph I. Chu

Examiner (ID: 12496, Phone: (571)270-1145 , Office: P/2666 )

Most Active Art Unit
2666
Art Unit(s)
2624, 2666, 2663, 2668, 2667
Total Applications
974
Issued Applications
744
Pending Applications
78
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17745635 [patent_doc_number] => 11393716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Devices including stair step structures, and related apparatuses and memory devices [patent_app_type] => utility [patent_app_number] => 16/945242 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 9192 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945242 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945242
Devices including stair step structures, and related apparatuses and memory devices Jul 30, 2020 Issued
Array ( [id] => 16981535 [patent_doc_number] => 20210225772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => SEMICONDUCTOR PACKAGE WITH BARRIER LAYER [patent_app_type] => utility [patent_app_number] => 16/929956 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929956
Semiconductor package with barrier layer Jul 14, 2020 Issued
Array ( [id] => 17493471 [patent_doc_number] => 11282785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Wireless charging package with chip integrated in coil center [patent_app_type] => utility [patent_app_number] => 16/927681 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927681
Wireless charging package with chip integrated in coil center Jul 12, 2020 Issued
Array ( [id] => 16402366 [patent_doc_number] => 20200343224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => Semiconductor Packages and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 16/927265 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927265
Semiconductor packages and methods of forming same Jul 12, 2020 Issued
Array ( [id] => 16394509 [patent_doc_number] => 20200335450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => HYBRID BONDING USING DUMMY BONDING CONTACTS AND DUMMY INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/924042 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924042
Hybrid bonding using dummy bonding contacts and dummy interconnects Jul 7, 2020 Issued
Array ( [id] => 16578768 [patent_doc_number] => 20210013169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD OF THE DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/923766 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923766
DISPLAY PANEL AND MANUFACTURING METHOD OF THE DISPLAY PANEL Jul 7, 2020 Abandoned
Array ( [id] => 17730766 [patent_doc_number] => 11387167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Semiconductor structure and manufacturing method for the same [patent_app_type] => utility [patent_app_number] => 16/920430 [patent_app_country] => US [patent_app_date] => 2020-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920430
Semiconductor structure and manufacturing method for the same Jul 2, 2020 Issued
Array ( [id] => 16364464 [patent_doc_number] => 20200321215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => METHOD AND STRUCTURE FOR CUTTING DENSE LINE PATTERNS USING SELF-ALIGNED DOUBLE PATTERNING [patent_app_type] => utility [patent_app_number] => 16/909510 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909510
Method and structure for cutting dense line patterns using self-aligned double patterning Jun 22, 2020 Issued
Array ( [id] => 17295475 [patent_doc_number] => 20210391314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 16/901682 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901682 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901682
Semiconductor packages and methods of forming same Jun 14, 2020 Issued
Array ( [id] => 17381151 [patent_doc_number] => 11239184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Package substrate, electronic device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/899507 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899507 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899507
Package substrate, electronic device package and method for manufacturing the same Jun 10, 2020 Issued
Array ( [id] => 17623208 [patent_doc_number] => 11342272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Substrate structures, and methods for forming the same and semiconductor package structures [patent_app_type] => utility [patent_app_number] => 16/899517 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7116 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899517
Substrate structures, and methods for forming the same and semiconductor package structures Jun 10, 2020 Issued
Array ( [id] => 16332365 [patent_doc_number] => 20200303331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => MANUFACTURING METHOD OF SEMICONDCUTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/893422 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893422
Manufacturing method of semicondcutor package Jun 3, 2020 Issued
Array ( [id] => 16316242 [patent_doc_number] => 20200294980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => MODULE [patent_app_type] => utility [patent_app_number] => 16/891206 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891206
Module Jun 2, 2020 Issued
Array ( [id] => 16316207 [patent_doc_number] => 20200294945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND RELATED MICROELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 16/890546 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890546 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890546
Apparatuses including redistribution layers and related microelectronic devices Jun 1, 2020 Issued
Array ( [id] => 16881099 [patent_doc_number] => 11031256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Semiconductor device with tiered pillar and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/887590 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6751 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887590
Semiconductor device with tiered pillar and manufacturing method thereof May 28, 2020 Issued
Array ( [id] => 17516871 [patent_doc_number] => 11296032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/885384 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 10117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885384
Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same May 27, 2020 Issued
Array ( [id] => 17181360 [patent_doc_number] => 11158609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Three-dimensional integrated package device for high-voltage silicon carbide power module [patent_app_type] => utility [patent_app_number] => 16/882301 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4167 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 553 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882301 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882301
Three-dimensional integrated package device for high-voltage silicon carbide power module May 21, 2020 Issued
Array ( [id] => 17310244 [patent_doc_number] => 11211371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 16/882191 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 12319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882191 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882191
Integrated circuit package and method May 21, 2020 Issued
Array ( [id] => 17166207 [patent_doc_number] => 11152319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Micro-connection structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/871032 [patent_app_country] => US [patent_app_date] => 2020-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 9060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871032 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871032
Micro-connection structure and manufacturing method thereof May 9, 2020 Issued
Array ( [id] => 16677445 [patent_doc_number] => 20210066211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/865432 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/865432
Package structure and method of fabricating the same May 3, 2020 Issued
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