Randolph I. Chu

Array ( [id] => 17152554 [patent_doc_number] => 11145645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Multi-stack three-dimensional memory devices [patent_app_type] => utility [patent_app_number] => 16/783152 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 12732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16348162 [patent_doc_number] => 20200312813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/777903 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16746413 [patent_doc_number] => 10971414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/777819 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 8429 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16210417 [patent_doc_number] => 20200243407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => COMPOSITE MATERIAL AND A SEMICONDUCTOR CONTAINER MADE OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/777853 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17032831 [patent_doc_number] => 11094649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Semiconductor package structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/748559 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 4725 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15906045 [patent_doc_number] => 20200152543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Thermal Dissipation Through Seal Rings in 3DIC Structure [patent_app_type] => utility [patent_app_number] => 16/741243 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17174360 [patent_doc_number] => 20210328031 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-10-21 [patent_title] => STRUCTURES AND METHODS FOR NOISE ISOLATION IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/729704 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17174360 [patent_doc_number] => 20210328031 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-10-21 [patent_title] => STRUCTURES AND METHODS FOR NOISE ISOLATION IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/729704 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16988001 [patent_doc_number] => 11075184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Semiconductor package and method of fabricating semiconductor package [patent_app_type] => utility [patent_app_number] => 16/719995 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 8744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15775791 [patent_doc_number] => 20200118913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MODULE AND METHOD OF MANUFACTURING MODULE [patent_app_type] => utility [patent_app_number] => 16/716647 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15775871 [patent_doc_number] => 20200118953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/714814 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16394527 [patent_doc_number] => 20200335468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/713143 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16796141 [patent_doc_number] => 20210125958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => EMBEDDED COPPER STRUCTURE FOR MICROELECTRONICS PACKAGE [patent_app_type] => utility [patent_app_number] => 16/709750 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16888995 [patent_doc_number] => 20210175192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SELECTIVE RECESS OF INTERCONNECTS FOR PROBING HYBRID BOND DEVICES [patent_app_type] => utility [patent_app_number] => 16/703298 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16881157 [patent_doc_number] => 11031314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Spacer structure for double-sided-cooled power module and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/695987 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4155 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15688061 [patent_doc_number] => 20200098694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/696759 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16425092 [patent_doc_number] => 20200350290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => STACK PACKAGES INCLUDING A FAN-OUT SUB-PACKAGE [patent_app_type] => utility [patent_app_number] => 16/689659 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16803362 [patent_doc_number] => 10998316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Vertical memory device and method for fabricating vertical memory device [patent_app_type] => utility [patent_app_number] => 16/686455 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 35 [patent_no_of_words] => 12037 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16973631 [patent_doc_number] => 11069611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Liner-free and partial liner-free contact/via structures [patent_app_type] => utility [patent_app_number] => 16/685780 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7522 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17032835 [patent_doc_number] => 11094653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/682848 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9761 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682848 [rel_patent_id] =>[rel_patent_doc_number] =>)