Search

Randolph I. Chu

Examiner (ID: 12496, Phone: (571)270-1145 , Office: P/2666 )

Most Active Art Unit
2666
Art Unit(s)
2624, 2666, 2663, 2668, 2667
Total Applications
974
Issued Applications
744
Pending Applications
78
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15590061 [patent_doc_number] => 20200071565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => PLASMA POLYMERIZED THIN FILM HAVING LOW DIELECTRIC CONSTANT, DEVICE, AND METHOD OF PREPARING THIN FILM [patent_app_type] => utility [patent_app_number] => 16/549150 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549150
Plasma polymerized thin film having low dielectric constant, device, and method of preparing thin film Aug 22, 2019 Issued
Array ( [id] => 17077959 [patent_doc_number] => 11114374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Graphene enabled selective barrier layer formation [patent_app_type] => utility [patent_app_number] => 16/547847 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547847 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547847
Graphene enabled selective barrier layer formation Aug 21, 2019 Issued
Array ( [id] => 16660596 [patent_doc_number] => 20210057233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR PACKAGES WITH PATTERNS OF DIE-SPECIFIC INFORMATION [patent_app_type] => utility [patent_app_number] => 16/548126 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548126
Semiconductor packages with patterns of die-specific information Aug 21, 2019 Issued
Array ( [id] => 17032827 [patent_doc_number] => 11094645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Semiconductor device and method of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/534814 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534814
Semiconductor device and method of manufacturing a semiconductor device Aug 6, 2019 Issued
Array ( [id] => 15564333 [patent_doc_number] => 20200066578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => CONDUCTIVE PATTERNS, SEMICONDUCTOR DEVICES COMPRISING THE CONDUCTIVE PATTERNS, AND RELATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/531837 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531837
Semiconductor devices comprising conductive patterns of varying dimensions and related systems Aug 4, 2019 Issued
Array ( [id] => 15154465 [patent_doc_number] => 20190355710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => Package-on-Package Structures and Methods for Forming the Same [patent_app_type] => utility [patent_app_number] => 16/531535 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531535
Package-on-package structures and methods for forming the same Aug 4, 2019 Issued
Array ( [id] => 16789349 [patent_doc_number] => 10991788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Organic light emitting display apparatus [patent_app_type] => utility [patent_app_number] => 16/527608 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527608 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527608
Organic light emitting display apparatus Jul 30, 2019 Issued
Array ( [id] => 15154317 [patent_doc_number] => 20190355636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS [patent_app_type] => utility [patent_app_number] => 16/526497 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526497
Package power delivery using plane and shaped vias Jul 29, 2019 Issued
Array ( [id] => 16553206 [patent_doc_number] => 10886373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Composite oxide semiconductor and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/511562 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 114 [patent_no_of_words] => 40336 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511562
Composite oxide semiconductor and method for manufacturing the same Jul 14, 2019 Issued
Array ( [id] => 16324216 [patent_doc_number] => 10784188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Methods and apparatus for a semiconductor device having bi-material die attach layer [patent_app_type] => utility [patent_app_number] => 16/443653 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5280 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443653
Methods and apparatus for a semiconductor device having bi-material die attach layer Jun 16, 2019 Issued
Array ( [id] => 16487800 [patent_doc_number] => 20200381409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/425354 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/425354
Semiconductor package and method for manufacturing the same May 28, 2019 Issued
Array ( [id] => 16487735 [patent_doc_number] => 20200381344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SPLIT CONDUCTIVE PAD FOR DEVICE TERMINAL [patent_app_type] => utility [patent_app_number] => 16/424700 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/424700
Split conductive pad for device terminal May 28, 2019 Issued
Array ( [id] => 16487745 [patent_doc_number] => 20200381354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => METALLIZATION INTERCONNECT STRUCTURE FORMATION [patent_app_type] => utility [patent_app_number] => 16/425524 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/425524
Metallization interconnect structure formation May 28, 2019 Issued
Array ( [id] => 16000881 [patent_doc_number] => 20200176311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => ARRANGEMENT METHOD AND ARRANGEMENT STRUCTURE OF CONDUCTIVE MATERIAL, AND LED DISPLAY THEREOF [patent_app_type] => utility [patent_app_number] => 16/424883 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424883 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/424883
ARRANGEMENT METHOD AND ARRANGEMENT STRUCTURE OF CONDUCTIVE MATERIAL, AND LED DISPLAY THEREOF May 28, 2019 Abandoned
Array ( [id] => 16707674 [patent_doc_number] => 10957618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Thermally conductive electronic packaging [patent_app_type] => utility [patent_app_number] => 16/425063 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/425063
Thermally conductive electronic packaging May 28, 2019 Issued
Array ( [id] => 16846015 [patent_doc_number] => 11018111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Wafer level derived flip chip package [patent_app_type] => utility [patent_app_number] => 16/423104 [patent_app_country] => US [patent_app_date] => 2019-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/423104
Wafer level derived flip chip package May 26, 2019 Issued
Array ( [id] => 16653393 [patent_doc_number] => 10930586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Integrated fan-out package and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/416278 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416278
Integrated fan-out package and method of fabricating the same May 19, 2019 Issued
Array ( [id] => 14784849 [patent_doc_number] => 20190267322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => METHODS OF FORMING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/413470 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413470
Methods of forming semiconductor devices May 14, 2019 Issued
Array ( [id] => 14784811 [patent_doc_number] => 20190267303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/412822 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412822
Electronic component and method for manufacturing the same May 14, 2019 Issued
Array ( [id] => 16699870 [patent_doc_number] => 10950478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Info structure with copper pillar having reversed profile [patent_app_type] => utility [patent_app_number] => 16/410183 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410183
Info structure with copper pillar having reversed profile May 12, 2019 Issued
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