Search

Randolph I. Chu

Examiner (ID: 12496, Phone: (571)270-1145 , Office: P/2666 )

Most Active Art Unit
2666
Art Unit(s)
2624, 2666, 2663, 2668, 2667
Total Applications
974
Issued Applications
744
Pending Applications
78
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14587807 [patent_doc_number] => 20190221512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => SEMICONDUCTOR PACKAGE HAVING A CIRCUIT PATTERN [patent_app_type] => utility [patent_app_number] => 16/362936 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362936
Semiconductor package having a circuit pattern Mar 24, 2019 Issued
Array ( [id] => 14509401 [patent_doc_number] => 20190198355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Method of Manufacturing a Package Having a Power Semiconductor Chip [patent_app_type] => utility [patent_app_number] => 16/293246 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293246
Method of manufacturing a package having a power semiconductor chip Mar 4, 2019 Issued
Array ( [id] => 16464084 [patent_doc_number] => 10847444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Through electrode substrate and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/293272 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 8114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293272 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293272
Through electrode substrate and semiconductor device Mar 4, 2019 Issued
Array ( [id] => 16241623 [patent_doc_number] => 20200258857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => BONDED SEMICONDUCTOR STRUCTURES HAVING BONDING CONTACTS MADE OF INDIFFUSIBLE CONDUCTIVE MATERIALS AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/292273 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292273
Bonded semiconductor structures having bonding contacts made of indiffusible conductive materials and methods for forming the same Mar 3, 2019 Issued
Array ( [id] => 16210483 [patent_doc_number] => 20200243473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HYBRID BONDING USING DUMMY BONDING CONTACTS [patent_app_type] => utility [patent_app_number] => 16/292277 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292277
Hybrid bonding using dummy bonding contacts Mar 3, 2019 Issued
Array ( [id] => 16210465 [patent_doc_number] => 20200243455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HYBRID BONDING USING DUMMY BONDING CONTACTS AND DUMMY INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/292279 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292279 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292279
Hybrid bonding using dummy bonding contacts and dummy interconnects Mar 3, 2019 Issued
Array ( [id] => 16210483 [patent_doc_number] => 20200243473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HYBRID BONDING USING DUMMY BONDING CONTACTS [patent_app_type] => utility [patent_app_number] => 16/292277 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292277
Hybrid bonding using dummy bonding contacts Mar 3, 2019 Issued
Array ( [id] => 16210483 [patent_doc_number] => 20200243473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HYBRID BONDING USING DUMMY BONDING CONTACTS [patent_app_type] => utility [patent_app_number] => 16/292277 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292277
Hybrid bonding using dummy bonding contacts Mar 3, 2019 Issued
Array ( [id] => 16210483 [patent_doc_number] => 20200243473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => HYBRID BONDING USING DUMMY BONDING CONTACTS [patent_app_type] => utility [patent_app_number] => 16/292277 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292277
Hybrid bonding using dummy bonding contacts Mar 3, 2019 Issued
Array ( [id] => 17048011 [patent_doc_number] => 11101201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Semiconductor package having leads with a negative standoff [patent_app_type] => utility [patent_app_number] => 16/289972 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4985 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289972
Semiconductor package having leads with a negative standoff Feb 28, 2019 Issued
Array ( [id] => 16272373 [patent_doc_number] => 20200273861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => CO-INTEGRATION OF NON-VOLATILE MEMORY ON GATE-ALL-AROUND FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/286843 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286843 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286843
Co-integration of non-volatile memory on gate-all-around field effect transistor Feb 26, 2019 Issued
Array ( [id] => 14784823 [patent_doc_number] => 20190267309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Semiconductor Package and Method of Manufacturing a Semiconductor Package [patent_app_type] => utility [patent_app_number] => 16/287318 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287318 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287318
Semiconductor package and method of manufacturing a semiconductor package Feb 26, 2019 Issued
Array ( [id] => 14969095 [patent_doc_number] => 20190312026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => ESD PROTECTION DEVICE, SEMICONDUCTOR DEVICE THAT INCLUDES AN ESD PROTECTION DEVICE, AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/287031 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287031 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287031
ESD protection device, semiconductor device that includes an ESD protection device, and method of manufacturing same Feb 26, 2019 Issued
Array ( [id] => 15890361 [patent_doc_number] => 10651541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-12 [patent_title] => Package integrated waveguide [patent_app_type] => utility [patent_app_number] => 16/287226 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287226 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287226
Package integrated waveguide Feb 26, 2019 Issued
Array ( [id] => 15351703 [patent_doc_number] => 20200013743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => Semiconductor Package [patent_app_type] => utility [patent_app_number] => 16/287064 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287064 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287064
Semiconductor package Feb 26, 2019 Issued
Array ( [id] => 17077973 [patent_doc_number] => 11114388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Warpage control for microelectronics packages [patent_app_type] => utility [patent_app_number] => 16/280993 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8867 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280993
Warpage control for microelectronics packages Feb 19, 2019 Issued
Array ( [id] => 14446291 [patent_doc_number] => 20190181019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => METHOD OF RECONSTITUTED SUBSTRATE FORMATION FOR ADVANCED PACKAGING APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/276866 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16276866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/276866
METHOD OF RECONSTITUTED SUBSTRATE FORMATION FOR ADVANCED PACKAGING APPLICATIONS Feb 14, 2019 Abandoned
Array ( [id] => 16226298 [patent_doc_number] => 20200251415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => PACKAGE PANEL PROCESSING WITH INTEGRATED CERAMIC ISOLATION [patent_app_type] => utility [patent_app_number] => 16/263110 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263110 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263110
Package panel processing with integrated ceramic isolation Jan 30, 2019 Issued
Array ( [id] => 14382513 [patent_doc_number] => 20190165169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => METHOD FOR FORMING A LATERAL SUPER-JUNCTION MOSFET DEVICE AND TERMINATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/262695 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262695 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262695
Method for forming a lateral super-junction MOSFET device and termination structure Jan 29, 2019 Issued
Array ( [id] => 14350445 [patent_doc_number] => 20190157195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => PACKAGED SEMICONDUCTOR DEVICE WITH A PARTICLE ROUGHENED SURFACE [patent_app_type] => utility [patent_app_number] => 16/252412 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252412
Packaged semiconductor device with a particle roughened surface Jan 17, 2019 Issued
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