Search

Randolph I. Chu

Examiner (ID: 12496, Phone: (571)270-1145 , Office: P/2666 )

Most Active Art Unit
2666
Art Unit(s)
2624, 2666, 2663, 2668, 2667
Total Applications
974
Issued Applications
744
Pending Applications
78
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15745745 [patent_doc_number] => 20200111762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => DISPLAY PANEL, METHOD FOR MANUFACTURING THE DISPLAY PANEL, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/246535 [patent_app_country] => US [patent_app_date] => 2019-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246535
Display panel, method for manufacturing the display panel, and display device Jan 12, 2019 Issued
Array ( [id] => 16172809 [patent_doc_number] => 10714386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Integrated circuit interconnect structure having metal oxide adhesive layer [patent_app_type] => utility [patent_app_number] => 16/245228 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 10104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16245228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/245228
Integrated circuit interconnect structure having metal oxide adhesive layer Jan 9, 2019 Issued
Array ( [id] => 15803563 [patent_doc_number] => 20200124924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/243025 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243025 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/243025
ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE Jan 7, 2019 Abandoned
Array ( [id] => 14985273 [patent_doc_number] => 10446558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures and contact holes [patent_app_type] => utility [patent_app_number] => 16/234223 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 14294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234223
Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures and contact holes Dec 26, 2018 Issued
Array ( [id] => 14238077 [patent_doc_number] => 20190131211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => COOLED ELECTRONICS PACKAGE WITH STACKED POWER ELECTRONICS COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/233266 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/233266
Cooled electronics package with stacked power electronics components Dec 26, 2018 Issued
Array ( [id] => 16339242 [patent_doc_number] => 10790211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Wafer-level packaging method and package structure thereof [patent_app_type] => utility [patent_app_number] => 16/231733 [patent_app_country] => US [patent_app_date] => 2018-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 9268 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231733 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231733
Wafer-level packaging method and package structure thereof Dec 23, 2018 Issued
Array ( [id] => 16339276 [patent_doc_number] => 10790245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => High-frequency ceramic board and high-frequency semiconductor element package [patent_app_type] => utility [patent_app_number] => 16/230240 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 13817 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230240 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/230240
High-frequency ceramic board and high-frequency semiconductor element package Dec 20, 2018 Issued
Array ( [id] => 14317593 [patent_doc_number] => 20190148500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/228809 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228809
Semiconductor device Dec 20, 2018 Issued
Array ( [id] => 16372411 [patent_doc_number] => 10804177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Wafer-level packaging method and package structure thereof [patent_app_type] => utility [patent_app_number] => 16/230224 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230224 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/230224
Wafer-level packaging method and package structure thereof Dec 20, 2018 Issued
Array ( [id] => 16264606 [patent_doc_number] => 10756051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Wafer-level system packaging method and package structure [patent_app_type] => utility [patent_app_number] => 16/229360 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229360
Wafer-level system packaging method and package structure Dec 20, 2018 Issued
Array ( [id] => 14350397 [patent_doc_number] => 20190157171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/228814 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228814
Semiconductor device Dec 20, 2018 Issued
Array ( [id] => 16324257 [patent_doc_number] => 10784229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Wafer level package structure and wafer level packaging method [patent_app_type] => utility [patent_app_number] => 16/229850 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 11162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229850
Wafer level package structure and wafer level packaging method Dec 20, 2018 Issued
Array ( [id] => 14317125 [patent_doc_number] => 20190148266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 16/228585 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228585
Semiconductor structure and manufacturing method for the same Dec 19, 2018 Issued
Array ( [id] => 17381147 [patent_doc_number] => 11239180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Structure and formation method of package structure with stacked semiconductor dies [patent_app_type] => utility [patent_app_number] => 16/227449 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227449
Structure and formation method of package structure with stacked semiconductor dies Dec 19, 2018 Issued
Array ( [id] => 16218477 [patent_doc_number] => 10734299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Package with tilted interface between device die and encapsulating material [patent_app_type] => utility [patent_app_number] => 16/223783 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223783
Package with tilted interface between device die and encapsulating material Dec 17, 2018 Issued
Array ( [id] => 14221271 [patent_doc_number] => 20190123020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same [patent_app_type] => utility [patent_app_number] => 16/223700 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223700
Integrated fan-out package including voltage regulators and methods forming same Dec 17, 2018 Issued
Array ( [id] => 15889453 [patent_doc_number] => 10651079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/222488 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222488 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222488
Semiconductor device and manufacturing method thereof Dec 16, 2018 Issued
Array ( [id] => 14191211 [patent_doc_number] => 20190115311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/219981 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219981
Package structure and method of forming the same Dec 13, 2018 Issued
Array ( [id] => 16845990 [patent_doc_number] => 11018086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Passive devices in package-on-package structures and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/215731 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 2933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215731 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215731
Passive devices in package-on-package structures and methods for forming the same Dec 10, 2018 Issued
Array ( [id] => 16132519 [patent_doc_number] => 10700027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Semiconductor copper metallization structure and related methods [patent_app_type] => utility [patent_app_number] => 16/214428 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 3789 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214428
Semiconductor copper metallization structure and related methods Dec 9, 2018 Issued
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