Search

Rasem Mourad

Examiner (ID: 2323, Phone: (571)270-7770 , Office: P/2836 )

Most Active Art Unit
2836
Art Unit(s)
2836
Total Applications
602
Issued Applications
431
Pending Applications
49
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10982742 [patent_doc_number] => 20160179686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'MEMORY MANAGEMENT METHOD FOR SUPPORTING SHARED VIRTUAL MEMORIES WITH HYBRID PAGE TABLE UTILIZATION AND RELATED MACHINE READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/833139 [patent_app_country] => US [patent_app_date] => 2015-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4189 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833139 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833139
Memory management method for supporting shared virtual memories with hybrid page table utilization and related machine readable medium Aug 22, 2015 Issued
Array ( [id] => 11688138 [patent_doc_number] => 09686191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Performing read operations in network on a chip architecture' [patent_app_type] => utility [patent_app_number] => 14/832654 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 16386 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14832654 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/832654
Performing read operations in network on a chip architecture Aug 20, 2015 Issued
Array ( [id] => 11458800 [patent_doc_number] => 20170052706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'SCALABLE AND EFFICIENT ACCESS TO AND MANAGEMENT OF DATA AND RESOURCES IN A TIERED DATA STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/832925 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14832925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/832925
Scalable and efficient access to and management of data and resources in a tiered data storage system Aug 20, 2015 Issued
Array ( [id] => 10589398 [patent_doc_number] => 09311009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Memory with mixed cell array and system including the memory' [patent_app_type] => utility [patent_app_number] => 14/826305 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4017 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826305 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/826305
Memory with mixed cell array and system including the memory Aug 13, 2015 Issued
Array ( [id] => 10609922 [patent_doc_number] => 09329954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'False power failure alert impact mitigation' [patent_app_type] => utility [patent_app_number] => 14/815611 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5186 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815611 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/815611
False power failure alert impact mitigation Jul 30, 2015 Issued
Array ( [id] => 11396878 [patent_doc_number] => 20170017414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'System And Method For Implementing Hierarchical Distributed-Linked Lists For Network Devices' [patent_app_type] => utility [patent_app_number] => 14/800654 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8330 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800654 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800654
System And Method For Implementing Hierarchical Distributed-Linked Lists For Network Devices Jul 14, 2015 Abandoned
Array ( [id] => 11397031 [patent_doc_number] => 20170017567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'System And Method For Implementing Distributed-Linked Lists For Network Devices' [patent_app_type] => utility [patent_app_number] => 14/800649 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8330 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800649 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800649
System And Method For Implementing Distributed-Linked Lists For Network Devices Jul 14, 2015 Abandoned
Array ( [id] => 14298875 [patent_doc_number] => 10289564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Computer and memory region management method [patent_app_type] => utility [patent_app_number] => 15/741704 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5406 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15741704 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/741704
Computer and memory region management method Jul 7, 2015 Issued
Array ( [id] => 12214672 [patent_doc_number] => 09911487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Method and system for storing and recovering data from flash memory' [patent_app_type] => utility [patent_app_number] => 14/754838 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 15306 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754838 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754838
Method and system for storing and recovering data from flash memory Jun 29, 2015 Issued
Array ( [id] => 10376678 [patent_doc_number] => 20150261685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'SYSTEMS AND METHODS FOR BACKGROUND DESTAGING STORAGE TRACKS' [patent_app_type] => utility [patent_app_number] => 14/727409 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727409
Systems and methods for background destaging storage tracks May 31, 2015 Issued
Array ( [id] => 10603128 [patent_doc_number] => 09323694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Systems and methods for background destaging storage tracks' [patent_app_type] => utility [patent_app_number] => 14/727432 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727432 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727432
Systems and methods for background destaging storage tracks May 31, 2015 Issued
Array ( [id] => 11116964 [patent_doc_number] => 20160313938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'FINE GRAINED MEMORY PROTECTION TO THWART MEMORY OVERRUN ATTACKS' [patent_app_type] => utility [patent_app_number] => 14/696229 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7485 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696229 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696229
FINE GRAINED MEMORY PROTECTION TO THWART MEMORY OVERRUN ATTACKS Apr 23, 2015 Abandoned
Array ( [id] => 11116945 [patent_doc_number] => 20160313919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'SUB-BLOCK INPUT/OUTPUT (I/O) COMMANDS FOR STORAGE DEVICE INCLUDING BYTE STREAM BUFFER' [patent_app_type] => utility [patent_app_number] => 14/695583 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695583 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/695583
Sub-block input/output (I/O) commands for storage device including byte stream buffer Apr 23, 2015 Issued
Array ( [id] => 11577472 [patent_doc_number] => 09632731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Distributing capacity slices across storage system nodes' [patent_app_type] => utility [patent_app_number] => 14/695608 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695608 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/695608
Distributing capacity slices across storage system nodes Apr 23, 2015 Issued
Array ( [id] => 10998965 [patent_doc_number] => 20160195912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'ELECTRICAL DEVICE WITH DETACHABLE STORAGE MODULE' [patent_app_type] => utility [patent_app_number] => 14/693422 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6226 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14693422 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/693422
Electrical device with detachable storage module Apr 21, 2015 Issued
Array ( [id] => 10335430 [patent_doc_number] => 20150220435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH' [patent_app_type] => utility [patent_app_number] => 14/688996 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7417 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688996 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688996
High availability storage appliance Apr 15, 2015 Issued
Array ( [id] => 10401396 [patent_doc_number] => 20150286405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'DEVICES AND OPERATION METHODS FOR CONFIGURING DATA STROBE SIGNAL IN MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/677321 [patent_app_country] => US [patent_app_date] => 2015-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5646 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14677321 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/677321
Devices and operation methods for configuring data strobe signal in memory device Apr 1, 2015 Issued
Array ( [id] => 11659161 [patent_doc_number] => 09672163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Field lockable memory' [patent_app_type] => utility [patent_app_number] => 14/676252 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2132 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676252 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676252
Field lockable memory Mar 31, 2015 Issued
Array ( [id] => 10402436 [patent_doc_number] => 20150287445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'METHOD FOR CONTROLLING MEMORY DEVICE ASYNCHRONOUSLY WITH RESPECT TO SYSTEM CLOCK, AND RELATED MEMORY DEVICE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/676795 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5554 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676795 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676795
Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system Mar 31, 2015 Issued
Array ( [id] => 11431005 [patent_doc_number] => 09569322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Memory migration in presence of live memory traffic' [patent_app_type] => utility [patent_app_number] => 14/675376 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675376 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675376
Memory migration in presence of live memory traffic Mar 30, 2015 Issued
Menu