Search

Rasha K. Fayed

Examiner (ID: 19311, Phone: (571)270-3804 , Office: P/2479 )

Most Active Art Unit
2413
Art Unit(s)
2413, 2479
Total Applications
427
Issued Applications
252
Pending Applications
54
Abandoned Applications
138

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20034850 [patent_doc_number] => 20250173072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => PROCESSING-IN-MEMORY DEVICE BASED ON RESISTIVE MEMORY AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/961689 [patent_app_country] => US [patent_app_date] => 2024-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18961689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/961689
PROCESSING-IN-MEMORY DEVICE BASED ON RESISTIVE MEMORY AND METHOD THEREOF Nov 26, 2024 Pending
Array ( [id] => 19757798 [patent_doc_number] => 20250046363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SIGNAL PROCESSING CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/923604 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923604 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923604
SIGNAL PROCESSING CIRCUIT AND MEMORY Oct 21, 2024 Pending
Array ( [id] => 19726914 [patent_doc_number] => 20250029665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => ADAPTIVE PROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/906579 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906579
ADAPTIVE PROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM Oct 3, 2024 Pending
Array ( [id] => 19696122 [patent_doc_number] => 20250014667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/894510 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894510 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/894510
MEMORY CIRCUIT Sep 23, 2024 Pending
Array ( [id] => 20601504 [patent_doc_number] => 20260079513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => VOLTAGE REGULATOR [patent_app_type] => utility [patent_app_number] => 18/885082 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885082 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/885082
VOLTAGE REGULATOR Sep 12, 2024 Pending
Array ( [id] => 20588369 [patent_doc_number] => 20260073965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/830668 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830668
MEMORY DEVICE Sep 10, 2024 Pending
Array ( [id] => 20182120 [patent_doc_number] => 20250266078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/828789 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828789
SEMICONDUCTOR DEVICE AND MEMORY SYSTEM Sep 8, 2024 Pending
Array ( [id] => 19749191 [patent_doc_number] => 20250037756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SENSE AMPLIFIER WITH DIGIT LINE MULTIPLEXING [patent_app_type] => utility [patent_app_number] => 18/791706 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791706
SENSE AMPLIFIER WITH DIGIT LINE MULTIPLEXING Jul 31, 2024 Pending
Array ( [id] => 19992509 [patent_doc_number] => 20250130731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => PROGRAMMING DATA IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/786100 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786100
PROGRAMMING DATA IN MEMORY Jul 25, 2024 Pending
Array ( [id] => 19577320 [patent_doc_number] => 20240381612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => THREE-PORT SRAM CELL AND LAYOUT METHOD [patent_app_type] => utility [patent_app_number] => 18/782815 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782815
THREE-PORT SRAM CELL AND LAYOUT METHOD Jul 23, 2024 Pending
Array ( [id] => 19574861 [patent_doc_number] => 20240379153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => DYNAMIC BUFFER LIMIT FOR AT-RISK DATA [patent_app_type] => utility [patent_app_number] => 18/781804 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781804
DYNAMIC BUFFER LIMIT FOR AT-RISK DATA Jul 22, 2024 Pending
Array ( [id] => 20209433 [patent_doc_number] => 20250279153 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-09-04 [patent_title] => SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/775981 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775981
SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES Jul 16, 2024 Pending
Array ( [id] => 20209433 [patent_doc_number] => 20250279153 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-09-04 [patent_title] => SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/775981 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775981
SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES Jul 16, 2024 Pending
Array ( [id] => 19531495 [patent_doc_number] => 20240355397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => CHARGE LOSS COMPENSATION DURING READ OPERATIONS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/762228 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762228
Charge loss compensation during read operations in a memory device Jul 1, 2024 Issued
Array ( [id] => 20448129 [patent_doc_number] => 20260004854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/760123 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760123
MEMORY DEVICE AND MEMORY SYSTEM Jun 30, 2024 Pending
Array ( [id] => 19787090 [patent_doc_number] => 20250060769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/760350 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760350 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760350
LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME Jun 30, 2024 Pending
Array ( [id] => 20612564 [patent_doc_number] => 12588180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Four-poly-pitch SRAM cell with backside metal tracks [patent_app_type] => utility [patent_app_number] => 18/751938 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751938
Four-poly-pitch SRAM cell with backside metal tracks Jun 23, 2024 Issued
Array ( [id] => 19500131 [patent_doc_number] => 20240339149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO IMPROVE READ MARGIN AND TO ALLEVIATE THE NEED FOR MANAGING DEMARCATION READ VOLTAGES [patent_app_type] => utility [patent_app_number] => 18/749412 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749412
MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO IMPROVE READ MARGIN AND TO ALLEVIATE THE NEED FOR MANAGING DEMARCATION READ VOLTAGES Jun 19, 2024 Pending
Array ( [id] => 19726899 [patent_doc_number] => 20250029650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SEMICONDUCTOR DEVICE HAVING ROW DECODER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/749446 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749446
SEMICONDUCTOR DEVICE HAVING ROW DECODER CIRCUIT Jun 19, 2024 Pending
Array ( [id] => 20396681 [patent_doc_number] => 20250372156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/731026 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731026 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731026
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF May 30, 2024 Pending
Menu