Search

Rasha K. Fayed

Examiner (ID: 19311, Phone: (571)270-3804 , Office: P/2479 )

Most Active Art Unit
2413
Art Unit(s)
2413, 2479
Total Applications
427
Issued Applications
252
Pending Applications
54
Abandoned Applications
138

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19483721 [patent_doc_number] => 20240331763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => APPARATUSES AND METHODS FOR REDUCING STANDBY CURRENT IN MEMORY ARRAY ACCESS CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/591798 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591798
APPARATUSES AND METHODS FOR REDUCING STANDBY CURRENT IN MEMORY ARRAY ACCESS CIRCUITS Feb 28, 2024 Pending
Array ( [id] => 19237052 [patent_doc_number] => 20240194247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/587207 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587207
Apparatuses and methods for logic/memory devices Feb 25, 2024 Issued
Array ( [id] => 20495168 [patent_doc_number] => 12537044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor device and memory device including complementary delay circuits for maximizing operation efficiency while minimizing area occupied by delay circuits [patent_app_type] => utility [patent_app_number] => 18/581398 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581398
Semiconductor device and memory device including complementary delay circuits for maximizing operation efficiency while minimizing area occupied by delay circuits Feb 19, 2024 Issued
Array ( [id] => 20167618 [patent_doc_number] => 20250259665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => DELAY ADJUSTER BASED CLOCK QUALIFIER TIMING ENHANCEMENT FOR MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 18/439464 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439464
DELAY ADJUSTER BASED CLOCK QUALIFIER TIMING ENHANCEMENT FOR MEMORY INTERFACE Feb 11, 2024 Pending
Array ( [id] => 19384315 [patent_doc_number] => 20240274185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/438635 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438635
MEMORY SYSTEM Feb 11, 2024 Pending
Array ( [id] => 19175838 [patent_doc_number] => 20240161812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 18/415023 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415023 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415023
Integrated assemblies Jan 16, 2024 Issued
Array ( [id] => 20530173 [patent_doc_number] => 12548614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Memory device with receiver circuit to suppress impermissible strobe states and noise [patent_app_type] => utility [patent_app_number] => 18/413386 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4551 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413386
Memory device with receiver circuit to suppress impermissible strobe states and noise Jan 15, 2024 Issued
Array ( [id] => 19842557 [patent_doc_number] => 12254956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 18/412873 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412873
Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof Jan 14, 2024 Issued
Array ( [id] => 19406863 [patent_doc_number] => 20240290374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/409714 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409714
MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS Jan 9, 2024 Issued
Array ( [id] => 19500132 [patent_doc_number] => 20240339150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/406518 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406518 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406518
Semiconductor memory device for eliminating the impact of offset voltage and control method thereof Jan 7, 2024 Issued
Array ( [id] => 19269035 [patent_doc_number] => 20240212739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DATA DESTRUCTION [patent_app_type] => utility [patent_app_number] => 18/403569 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403569
DATA DESTRUCTION Jan 2, 2024 Pending
Array ( [id] => 20611024 [patent_doc_number] => 12586628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Adjusting pulse width based on address signal in memory devices [patent_app_type] => utility [patent_app_number] => 18/402107 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402107 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402107
Adjusting pulse width based on address signal in memory devices Jan 1, 2024 Issued
Array ( [id] => 20416638 [patent_doc_number] => 12499927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Memory device with receiver circuit to suppress noise on data strobe signals [patent_app_type] => utility [patent_app_number] => 18/395798 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4699 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395798
Memory device with receiver circuit to suppress noise on data strobe signals Dec 25, 2023 Issued
Array ( [id] => 19618899 [patent_doc_number] => 20240404579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => MEMORY DEVICES AND METHODS FOR DECODING ADDRESSES THEREOF [patent_app_type] => utility [patent_app_number] => 18/539472 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/539472
MEMORY DEVICES AND METHODS FOR DECODING ADDRESSES THEREOF Dec 13, 2023 Pending
Array ( [id] => 19085935 [patent_doc_number] => 20240112736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/536186 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536186
Adaptive bias decoder for non-volatile memory system Dec 10, 2023 Issued
Array ( [id] => 20189579 [patent_doc_number] => 12400701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Memory device for performing smart refresh operation and method of reducing power consumption during refresh [patent_app_type] => utility [patent_app_number] => 18/535647 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13046 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535647
Memory device for performing smart refresh operation and method of reducing power consumption during refresh Dec 10, 2023 Issued
Array ( [id] => 20416655 [patent_doc_number] => 12499945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Adaptive bias decoder for non-volatile memory system [patent_app_type] => utility [patent_app_number] => 18/536147 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 65 [patent_no_of_words] => 12966 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536147
Adaptive bias decoder for non-volatile memory system Dec 10, 2023 Issued
Array ( [id] => 20359946 [patent_doc_number] => 12475950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Adaptive bias decoder for non-volatile memory system [patent_app_type] => utility [patent_app_number] => 18/536123 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 65 [patent_no_of_words] => 12984 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536123
Adaptive bias decoder for non-volatile memory system Dec 10, 2023 Issued
Array ( [id] => 19285349 [patent_doc_number] => 20240221826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => FLASH MEMORY AND READ RECOVERY METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/523045 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523045
FLASH MEMORY AND READ RECOVERY METHOD THEREOF Nov 28, 2023 Pending
Array ( [id] => 19986751 [patent_doc_number] => 20250124973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => CONTROL UNIT OF MEMORY AND METHOD OF CONTROLLING MEMORY [patent_app_type] => utility [patent_app_number] => 18/518549 [patent_app_country] => US [patent_app_date] => 2023-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518549
Method for adjusting logic states of data strobe signals used by memory device Nov 22, 2023 Issued
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