Search

Rasha K. Fayed

Examiner (ID: 19311, Phone: (571)270-3804 , Office: P/2479 )

Most Active Art Unit
2413
Art Unit(s)
2413, 2479
Total Applications
427
Issued Applications
252
Pending Applications
54
Abandoned Applications
138

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20345807 [patent_doc_number] => 12469542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Semiconductor memory device with multiple banks each including decoding circuit controlled by memory-bank select signals [patent_app_type] => utility [patent_app_number] => 18/362911 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362911 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362911
Semiconductor memory device with multiple banks each including decoding circuit controlled by memory-bank select signals Jul 30, 2023 Issued
Array ( [id] => 20215966 [patent_doc_number] => 12412620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Second word line combined with y-mux signal in high voltage memory program [patent_app_type] => utility [patent_app_number] => 18/361559 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361559 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361559
Second word line combined with y-mux signal in high voltage memory program Jul 27, 2023 Issued
Array ( [id] => 18926765 [patent_doc_number] => 20240029769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => Multi-Stage Bit Line Pre-Charge [patent_app_type] => utility [patent_app_number] => 18/359079 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359079
Multi-stage bit line pre-charge Jul 25, 2023 Issued
Array ( [id] => 18791151 [patent_doc_number] => 20230380138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/226096 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226096
Semiconductor element memory device Jul 24, 2023 Issued
Array ( [id] => 18774004 [patent_doc_number] => 20230368834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => Apparatus for Page-copy Data Accessing [patent_app_type] => utility [patent_app_number] => 18/226228 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226228
Apparatus for page-copy data accessing Jul 24, 2023 Issued
Array ( [id] => 19420758 [patent_doc_number] => 20240296882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => INDEPENDENT PLANE CONCURRENT MEMORY OPERATION IN NON-VOLATILE MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/224202 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224202
INDEPENDENT PLANE CONCURRENT MEMORY OPERATION IN NON-VOLATILE MEMORY STRUCTURES Jul 19, 2023 Pending
Array ( [id] => 19237046 [patent_doc_number] => 20240194241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DEVICE AND METHOD FOR CALIBRATING REFERENCE VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/223097 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223097 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223097
Reference voltage calibration method that enables stable and continuous data transmission regardless of operating conditions Jul 17, 2023 Issued
Array ( [id] => 20189584 [patent_doc_number] => 12400706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => In memory searching device [patent_app_type] => utility [patent_app_number] => 18/347571 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347571
In memory searching device Jul 5, 2023 Issued
Array ( [id] => 19356701 [patent_doc_number] => 12057156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Quadrature error correction circuit and semiconductor memory device including the same [patent_app_type] => utility [patent_app_number] => 18/218243 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 16141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218243
Quadrature error correction circuit and semiconductor memory device including the same Jul 4, 2023 Issued
Array ( [id] => 18743092 [patent_doc_number] => 20230352080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SENSE AMPLIFIER WITH DIGIT LINE MULTIPLEXING [patent_app_type] => utility [patent_app_number] => 18/217205 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217205
Sense amplifier with digit line multiplexing Jun 29, 2023 Issued
Array ( [id] => 18848486 [patent_doc_number] => 20230410890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Memory System Topologies Including A Memory Die Stack [patent_app_type] => utility [patent_app_number] => 18/340726 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340726
Memory system topologies including a memory die stack Jun 22, 2023 Issued
Array ( [id] => 18714774 [patent_doc_number] => 20230337418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/211807 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211807
MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME Jun 19, 2023 Pending
Array ( [id] => 19733587 [patent_doc_number] => 12211587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => SRAM with tracking circuitry for reducing active power [patent_app_type] => utility [patent_app_number] => 18/336418 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336418
SRAM with tracking circuitry for reducing active power Jun 15, 2023 Issued
Array ( [id] => 19646241 [patent_doc_number] => 20240420761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ENDURANCE, POWER, AND PERFORMANCE IMPROVEMENT LOGIC FOR A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 18/333916 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333916
ENDURANCE, POWER, AND PERFORMANCE IMPROVEMENT LOGIC FOR A MEMORY ARRAY Jun 12, 2023 Pending
Array ( [id] => 19634344 [patent_doc_number] => 20240412793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => NON-VOLATILE MEMORY AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/329583 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329583
NON-VOLATILE MEMORY AND PROGRAMMING METHOD THEREOF Jun 5, 2023 Pending
Array ( [id] => 19679068 [patent_doc_number] => 12190939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory subword driver circuits and layout [patent_app_type] => utility [patent_app_number] => 18/313948 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313948
Memory subword driver circuits and layout May 7, 2023 Issued
Array ( [id] => 19260674 [patent_doc_number] => 12020739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Memory device for reducing row hammer disturbance, and a method of refreshing the same [patent_app_type] => utility [patent_app_number] => 18/138849 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9076 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138849
Memory device for reducing row hammer disturbance, and a method of refreshing the same Apr 24, 2023 Issued
Array ( [id] => 20215955 [patent_doc_number] => 12412609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Method of reducing program disturbance in memory device and memory device utilizing same [patent_app_type] => utility [patent_app_number] => 18/139316 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 3736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139316
Method of reducing program disturbance in memory device and memory device utilizing same Apr 24, 2023 Issued
Array ( [id] => 19531477 [patent_doc_number] => 20240355379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => Voltage Range for Training Physical Memory [patent_app_type] => utility [patent_app_number] => 18/305080 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305080
Voltage Range for Training Physical Memory Apr 20, 2023 Pending
Array ( [id] => 18812227 [patent_doc_number] => 20230386564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPERATION BY ACCOUNTING FOR VARIATION IN READ CURRENT [patent_app_type] => utility [patent_app_number] => 18/137159 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/137159
Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current Apr 19, 2023 Issued
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