Search

Rashid A. Alam

Examiner (ID: 16828, Phone: (571)270-3959 , Office: P/1721 )

Most Active Art Unit
1721
Art Unit(s)
1795, 1747, 1722, 1721
Total Applications
526
Issued Applications
361
Pending Applications
0
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19057001 [patent_doc_number] => 20240098970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY [patent_app_type] => utility [patent_app_number] => 17/946925 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946925
Vertical digit lines with alternating epitaxial silicon for horizontal access devices in 3D memory Sep 15, 2022 Issued
Array ( [id] => 19945331 [patent_doc_number] => 12317481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => 3D memory with cell stacking using an in-situ capacitor stack [patent_app_type] => utility [patent_app_number] => 17/946715 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 2195 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946715
3D memory with cell stacking using an in-situ capacitor stack Sep 15, 2022 Issued
Array ( [id] => 20119567 [patent_doc_number] => 12369305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor structure, method for manufacturing same and memory [patent_app_type] => utility [patent_app_number] => 17/944814 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 5365 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944814
Semiconductor structure, method for manufacturing same and memory Sep 13, 2022 Issued
Array ( [id] => 20260531 [patent_doc_number] => 12432902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor structure, method for forming semiconductor structure, and memory [patent_app_type] => utility [patent_app_number] => 17/940577 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 7120 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940577 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940577
Semiconductor structure, method for forming semiconductor structure, and memory Sep 7, 2022 Issued
Array ( [id] => 19040378 [patent_doc_number] => 20240090193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/940365 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940365
SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Sep 7, 2022 Pending
Array ( [id] => 20390676 [patent_doc_number] => 12490423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor structure and method for manufacturing semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/940952 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 5453 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940952 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940952
Semiconductor structure and method for manufacturing semiconductor structure Sep 7, 2022 Issued
Array ( [id] => 19966631 [patent_doc_number] => 12336168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Method of manufacturing semiconductor structure and semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/929842 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 2257 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929842
Method of manufacturing semiconductor structure and semiconductor structure Sep 5, 2022 Issued
Array ( [id] => 19913674 [patent_doc_number] => 12289907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Vertical inverter and semiconductor device [patent_app_type] => utility [patent_app_number] => 17/910256 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3480 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17910256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/910256
Vertical inverter and semiconductor device Aug 29, 2022 Issued
Array ( [id] => 18745580 [patent_doc_number] => 20230354574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => METHOD OF MANUFACTURING CAPACITOR, CAPACITOR, AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/822815 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822815
Method of manufacturing capacitor, capacitor, and memory Aug 28, 2022 Issued
Array ( [id] => 19237490 [patent_doc_number] => 20240194685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DRIVING SUBSTRATE, METHOD FOR FABRICATING SAME, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/802975 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17802975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/802975
Driving substrate, method for fabricating same, and display panel Aug 14, 2022 Issued
Array ( [id] => 19285917 [patent_doc_number] => 20240222394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ARRAY SUBSTRATE AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/905258 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17905258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/905258
Array substrate and display panel Aug 11, 2022 Issued
Array ( [id] => 18040429 [patent_doc_number] => 20220384646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => METHOD OF MAKING AN INTEGRATED CIRCUIT WITH DRAIN WELL HAVING MULTIPLE ZONES [patent_app_type] => utility [patent_app_number] => 17/884872 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884872
Method of making an integrated circuit with drain well having multiple zones Aug 9, 2022 Issued
Array ( [id] => 20443049 [patent_doc_number] => 12513895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Semiconductor structure and method for preparing same [patent_app_type] => utility [patent_app_number] => 17/879039 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 3453 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879039
Semiconductor structure and method for preparing same Aug 1, 2022 Issued
Array ( [id] => 18254637 [patent_doc_number] => 20230081676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/878397 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878397
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE Jul 31, 2022 Pending
Array ( [id] => 18814960 [patent_doc_number] => 20230389298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/816438 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816438
Semiconductor structure and manufacturing method thereof Jul 31, 2022 Issued
Array ( [id] => 18935633 [patent_doc_number] => 11888079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Electrical devices making use of counterdoped junctions [patent_app_type] => utility [patent_app_number] => 17/877914 [patent_app_country] => US [patent_app_date] => 2022-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 75 [patent_no_of_words] => 23799 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877914 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877914
Electrical devices making use of counterdoped junctions Jul 29, 2022 Issued
Array ( [id] => 18929279 [patent_doc_number] => 20240032283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 17/870073 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870073 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870073
Semiconductor device with air gap and method for preparing the same Jul 20, 2022 Issued
Array ( [id] => 18024295 [patent_doc_number] => 20220375794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => FIN FIELD EFFECT TRANSISTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/870182 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870182
Fin field effect transistor device structure Jul 20, 2022 Issued
Array ( [id] => 18556996 [patent_doc_number] => 20230255015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/863991 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863991
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Jul 12, 2022 Pending
Array ( [id] => 18081178 [patent_doc_number] => 20220406790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Silicon-Containing Layer for Bit Line Resistance Reduction [patent_app_type] => utility [patent_app_number] => 17/861412 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861412
Silicon-containing layer for bit line resistance reduction Jul 10, 2022 Issued
Menu