
Ratisha Mehta
Examiner (ID: 14034, Phone: (571)270-7473 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 2817, 2895 |
| Total Applications | 826 |
| Issued Applications | 703 |
| Pending Applications | 60 |
| Abandoned Applications | 83 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17971454
[patent_doc_number] => 11489004
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-01
[patent_title] => Display substrate, method for manufacturing same, and display device thereof
[patent_app_type] => utility
[patent_app_number] => 16/620542
[patent_app_country] => US
[patent_app_date] => 2019-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2908
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16620542
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/620542 | Display substrate, method for manufacturing same, and display device thereof | Nov 3, 2019 | Issued |
Array
(
[id] => 15564373
[patent_doc_number] => 20200066598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/672984
[patent_app_country] => US
[patent_app_date] => 2019-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9288
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672984
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/672984 | Semiconductor structure and manufacturing method thereof | Nov 3, 2019 | Issued |
Array
(
[id] => 19428454
[patent_doc_number] => 12087892
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Supporting backplane, manufacturing method therefor and backplane
[patent_app_type] => utility
[patent_app_number] => 17/043937
[patent_app_country] => US
[patent_app_date] => 2019-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 5993
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17043937
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/043937 | Supporting backplane, manufacturing method therefor and backplane | Oct 30, 2019 | Issued |
Array
(
[id] => 16536827
[patent_doc_number] => 10879444
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods
[patent_app_type] => utility
[patent_app_number] => 16/669785
[patent_app_country] => US
[patent_app_date] => 2019-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 5730
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669785
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/669785 | Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods | Oct 30, 2019 | Issued |
Array
(
[id] => 17188877
[patent_doc_number] => 20210335762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => DISPLAY PANEL, DISPLAY MODULE, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/619482
[patent_app_country] => US
[patent_app_date] => 2019-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4819
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16619482
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/619482 | Display panel, display module, and display device | Oct 29, 2019 | Issued |
Array
(
[id] => 15504547
[patent_doc_number] => 20200052462
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => METHOD OF MANUFACTURING LIGHT EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/660503
[patent_app_country] => US
[patent_app_date] => 2019-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9874
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660503
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/660503 | Method of manufacturing light emitting device | Oct 21, 2019 | Issued |
Array
(
[id] => 15873379
[patent_doc_number] => 20200144093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-07
[patent_title] => METHOD FOR MANUFACTURING LAMINATE AND METHOD FOR MANUFACTURING SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 16/655499
[patent_app_country] => US
[patent_app_date] => 2019-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655499
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/655499 | Method for manufacturing laminate and method for manufacturing substrate | Oct 16, 2019 | Issued |
Array
(
[id] => 17648924
[patent_doc_number] => 11351635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-07
[patent_title] => Apparatus and method for directional etch with micron zone beam and angle control
[patent_app_type] => utility
[patent_app_number] => 16/653401
[patent_app_country] => US
[patent_app_date] => 2019-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5975
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653401
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/653401 | Apparatus and method for directional etch with micron zone beam and angle control | Oct 14, 2019 | Issued |
Array
(
[id] => 19370650
[patent_doc_number] => 12062744
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Display substrate, display device and method for manufacturing a display substrate
[patent_app_type] => utility
[patent_app_number] => 16/975771
[patent_app_country] => US
[patent_app_date] => 2019-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 30
[patent_no_of_words] => 6409
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16975771
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/975771 | Display substrate, display device and method for manufacturing a display substrate | Oct 11, 2019 | Issued |
Array
(
[id] => 16379520
[patent_doc_number] => 20200328363
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/591141
[patent_app_country] => US
[patent_app_date] => 2019-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12256
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591141
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/591141 | Display panel and display device | Oct 1, 2019 | Issued |
Array
(
[id] => 17152417
[patent_doc_number] => 11145506
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-12
[patent_title] => Selective passivation and selective deposition
[patent_app_type] => utility
[patent_app_number] => 16/588600
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 31
[patent_no_of_words] => 19775
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588600
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/588600 | Selective passivation and selective deposition | Sep 29, 2019 | Issued |
Array
(
[id] => 15746217
[patent_doc_number] => 20200111998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-09
[patent_title] => METHOD FOR FORMING STACKED STRUCTURE BONDED BETWEEN INNER LAYERS BY ELECTROSTATIC FORCE AND METHOD FOR MANUFACTURING DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/585420
[patent_app_country] => US
[patent_app_date] => 2019-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7348
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585420
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/585420 | METHOD FOR FORMING STACKED STRUCTURE BONDED BETWEEN INNER LAYERS BY ELECTROSTATIC FORCE AND METHOD FOR MANUFACTURING DISPLAY DEVICE | Sep 26, 2019 | Abandoned |
Array
(
[id] => 16479669
[patent_doc_number] => 10854625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-01
[patent_title] => Method of integrating a charge-trapping gate stack into a CMOS flow
[patent_app_type] => utility
[patent_app_number] => 16/578850
[patent_app_country] => US
[patent_app_date] => 2019-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 5717
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578850
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/578850 | Method of integrating a charge-trapping gate stack into a CMOS flow | Sep 22, 2019 | Issued |
Array
(
[id] => 17166457
[patent_doc_number] => 11152570
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Electronic component manufacturing method
[patent_app_type] => utility
[patent_app_number] => 16/578022
[patent_app_country] => US
[patent_app_date] => 2019-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 3122
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578022
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/578022 | Electronic component manufacturing method | Sep 19, 2019 | Issued |
Array
(
[id] => 16773973
[patent_doc_number] => 10985094
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-20
[patent_title] => Lead frame and method of manufacturing lead frame
[patent_app_type] => utility
[patent_app_number] => 16/571304
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 35
[patent_no_of_words] => 7838
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571304
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571304 | Lead frame and method of manufacturing lead frame | Sep 15, 2019 | Issued |
Array
(
[id] => 16715908
[patent_doc_number] => 20210083055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => Gate All Around Transistors with Different Threshold Voltages
[patent_app_type] => utility
[patent_app_number] => 16/571289
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7767
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571289
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571289 | Gate all around transistors with different threshold voltages | Sep 15, 2019 | Issued |
Array
(
[id] => 15657331
[patent_doc_number] => 20200091196
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-19
[patent_title] => THIN-FILM TRANSISTOR SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND LIQUID CRYSTAL DISPLAY
[patent_app_type] => utility
[patent_app_number] => 16/570840
[patent_app_country] => US
[patent_app_date] => 2019-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14582
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570840
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/570840 | THIN-FILM TRANSISTOR SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND LIQUID CRYSTAL DISPLAY | Sep 12, 2019 | Abandoned |
Array
(
[id] => 15597909
[patent_doc_number] => 20200075489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => POWER DISTRIBUTION NETWORK FOR 3D LOGIC AND MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/560544
[patent_app_country] => US
[patent_app_date] => 2019-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5380
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560544
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/560544 | Power distribution network for 3D logic and memory | Sep 3, 2019 | Issued |
Array
(
[id] => 17847937
[patent_doc_number] => 11437322
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-06
[patent_title] => Semiconductor device package
[patent_app_type] => utility
[patent_app_number] => 16/560862
[patent_app_country] => US
[patent_app_date] => 2019-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 5074
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560862
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/560862 | Semiconductor device package | Sep 3, 2019 | Issued |
Array
(
[id] => 17963973
[patent_doc_number] => 20220344554
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => BACKPLANE, BACKLIGHT SOURCE, DISPLAY DEVICE AND MANUFACTURING METHOD OF BACKPLANE
[patent_app_type] => utility
[patent_app_number] => 16/957766
[patent_app_country] => US
[patent_app_date] => 2019-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16957766
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/957766 | Backplane, backlight source, display device and manufacturing method of backplane | Aug 29, 2019 | Issued |