Search

Raymond Mah

Examiner (ID: 5124)

Most Active Art Unit
2215
Art Unit(s)
2875, 2215, 2605, 2607, 2618, 2613, 2608, 2899
Total Applications
347
Issued Applications
282
Pending Applications
8
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20019210 [patent_doc_number] => 20250157432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE [patent_app_type] => utility [patent_app_number] => 19/021963 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19021963 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/021963
SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE Jan 14, 2025 Pending
Array ( [id] => 20009246 [patent_doc_number] => 20250147468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => TIME TO DIGITAL CONVERTER (TDC) CIRCUIT WITH SELF-ADAPTIVE TIME GRANULARITY AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 19/018950 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018950 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018950
TIME TO DIGITAL CONVERTER (TDC) CIRCUIT WITH SELF-ADAPTIVE TIME GRANULARITY AND RELATED METHODS Jan 12, 2025 Pending
Array ( [id] => 20124973 [patent_doc_number] => 20250240004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => A Method for Enhancing Controllability on Switching Speed of Electronic Cascode Power Device [patent_app_type] => utility [patent_app_number] => 19/008638 [patent_app_country] => US [patent_app_date] => 2025-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008638 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/008638
A Method for Enhancing Controllability on Switching Speed of Electronic Cascode Power Device Jan 2, 2025 Pending
Array ( [id] => 20589087 [patent_doc_number] => 20260074684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => DELAY LOCKED LOOP CIRCUIT AND OPERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/991700 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/991700
DELAY LOCKED LOOP CIRCUIT AND OPERATING METHOD Dec 22, 2024 Pending
Array ( [id] => 20069953 [patent_doc_number] => 20250208175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => CURRENT SENSING CIRCUITS AND METHOD [patent_app_type] => utility [patent_app_number] => 18/989251 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18989251 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/989251
CURRENT SENSING CIRCUITS AND METHOD Dec 19, 2024 Pending
Array ( [id] => 19987587 [patent_doc_number] => 20250125809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => CHARGE PUMP, PHASE-LOCKED LOOP, RADAR SENSOR, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/988112 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18988112 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/988112
CHARGE PUMP, PHASE-LOCKED LOOP, RADAR SENSOR, AND ELECTRONIC DEVICE Dec 18, 2024 Pending
Array ( [id] => 20572956 [patent_doc_number] => 20260066885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/981100 [patent_app_country] => US [patent_app_date] => 2024-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18981100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/981100
SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY SYSTEM Dec 12, 2024 Pending
Array ( [id] => 20054448 [patent_doc_number] => 20250192670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => INTEGRATED GAN POWER DEVICES INCLUDING PFC AND QR FLYBACK CONTROLLERS [patent_app_type] => utility [patent_app_number] => 18/975373 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18975373 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/975373
INTEGRATED GAN POWER DEVICES INCLUDING PFC AND QR FLYBACK CONTROLLERS Dec 9, 2024 Pending
Array ( [id] => 19994534 [patent_doc_number] => 20250132756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => METHODS AND DEVICES FOR FAST SWITCHING OF RADIO FREQUENCY SWITCHES [patent_app_type] => utility [patent_app_number] => 18/964292 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964292 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/964292
METHODS AND DEVICES FOR FAST SWITCHING OF RADIO FREQUENCY SWITCHES Nov 28, 2024 Pending
Array ( [id] => 20488935 [patent_doc_number] => 20260025137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/963511 [patent_app_country] => US [patent_app_date] => 2024-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18963511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/963511
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SEMICONDUCTOR DEVICE Nov 27, 2024 Pending
Array ( [id] => 20089691 [patent_doc_number] => 20250219627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => HARMONICS CANCELLATION CIRCUIT AND APPARATUS FOR VECTOR SYNTHESIS USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/958282 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958282
HARMONICS CANCELLATION CIRCUIT AND APPARATUS FOR VECTOR SYNTHESIS USING THE SAME Nov 24, 2024 Pending
Array ( [id] => 20674510 [patent_doc_number] => 12615037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Multi-master control circuit [patent_app_type] => utility [patent_app_number] => 18/929257 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929257 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929257
Multi-master control circuit Oct 27, 2024 Issued
Array ( [id] => 20020376 [patent_doc_number] => 20250158598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SIGNAL SAMPLING DEVICE FOR LOW VOLTAGE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/926559 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926559 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926559
SIGNAL SAMPLING DEVICE FOR LOW VOLTAGE APPLICATIONS Oct 24, 2024 Pending
Array ( [id] => 20291902 [patent_doc_number] => 20250317145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => BUFFER CIRCUIT HAVING ENHANCED SLEW RATE [patent_app_type] => utility [patent_app_number] => 18/904388 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904388 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/904388
BUFFER CIRCUIT HAVING ENHANCED SLEW RATE Oct 1, 2024 Pending
Array ( [id] => 20103644 [patent_doc_number] => 20250233580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => SECURITY CHIP AND CLOCK GATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/823786 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823786
SECURITY CHIP AND CLOCK GATING METHOD THEREOF Sep 3, 2024 Pending
Array ( [id] => 20572960 [patent_doc_number] => 20260066889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => LOW-POWER LOW-AREA DEADTIME GENERATOR [patent_app_type] => utility [patent_app_number] => 18/823924 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823924
LOW-POWER LOW-AREA DEADTIME GENERATOR Sep 3, 2024 Pending
Array ( [id] => 19661956 [patent_doc_number] => 20240429021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => HIGH POWER GENERATOR AND METHOD OF SUPPLYING HIGH POWER PULSES [patent_app_type] => utility [patent_app_number] => 18/817265 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817265
HIGH POWER GENERATOR AND METHOD OF SUPPLYING HIGH POWER PULSES Aug 27, 2024 Pending
Array ( [id] => 20545001 [patent_doc_number] => 20260051894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-19 [patent_title] => Digital Phase Alignment for Phase-Locked Loop (PLL) Circuitry [patent_app_type] => utility [patent_app_number] => 18/808949 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808949 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/808949
Digital Phase Alignment for Phase-Locked Loop (PLL) Circuitry Aug 18, 2024 Pending
Array ( [id] => 19605660 [patent_doc_number] => 20240396540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => INVERTER-BASED COMPARATOR [patent_app_type] => utility [patent_app_number] => 18/797259 [patent_app_country] => US [patent_app_date] => 2024-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797259
INVERTER-BASED COMPARATOR Aug 6, 2024 Pending
Array ( [id] => 19880377 [patent_doc_number] => 20250112634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => METHODS AND SYSTEMS OF OPERATING A DOUBLE-SIDED DOUBLE-BASE BIPOLAR JUNCTION TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/795582 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795582 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/795582
METHODS AND SYSTEMS OF OPERATING A DOUBLE-SIDED DOUBLE-BASE BIPOLAR JUNCTION TRANSISTOR Aug 5, 2024 Issued
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