Search

Raymond Ngan Phan

Examiner (ID: 6794)

Most Active Art Unit
2111
Art Unit(s)
2186, 2305, 2787, 2185, 2781, 2181, 2175, 2111
Total Applications
1838
Issued Applications
1676
Pending Applications
92
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19864305 [patent_doc_number] => 20250103091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => APPARATUSES AND METHODS FOR ADJUSTING SKEWS BETWEEN DATA AND CLOCK [patent_app_type] => utility [patent_app_number] => 18/756305 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756305 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756305
APPARATUSES AND METHODS FOR ADJUSTING SKEWS BETWEEN DATA AND CLOCK Jun 26, 2024 Pending
Array ( [id] => 19747614 [patent_doc_number] => 20250036179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => DISPLAY MOUNT [patent_app_type] => utility [patent_app_number] => 18/750596 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750596 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750596
DISPLAY MOUNT Jun 20, 2024 Pending
Array ( [id] => 19588297 [patent_doc_number] => 20240385854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHODS AND APPARATUS FOR CONFIGURING WEARABLE DEVICES [patent_app_type] => utility [patent_app_number] => 18/748964 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748964
METHODS AND APPARATUS FOR CONFIGURING WEARABLE DEVICES Jun 19, 2024 Pending
Array ( [id] => 20395050 [patent_doc_number] => 20250370525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => VERIFICATION OF POWER CABLE CHECK ON SERVER EQUIPMENT [patent_app_type] => utility [patent_app_number] => 18/675219 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675219
VERIFICATION OF POWER CABLE CHECK ON SERVER EQUIPMENT May 27, 2024 Pending
Array ( [id] => 19434387 [patent_doc_number] => 20240302885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => PATTERN-BASED ACTIVATION OF MEMORY POWER CONSUMPTION MODE [patent_app_type] => utility [patent_app_number] => 18/667548 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667548 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667548
Activation of memory power consumption mode based on pattern of power state change requests May 16, 2024 Issued
Array ( [id] => 20365670 [patent_doc_number] => 20250355482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => Method of Minimizing Rusting at a Power Interface of a Wearable Computing Device [patent_app_type] => utility [patent_app_number] => 18/663310 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663310
Method of Minimizing Rusting at a Power Interface of a Wearable Computing Device May 13, 2024 Pending
Array ( [id] => 20351596 [patent_doc_number] => 20250348448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => DERIVING SYSTEM CLOCK FROM GATED DATA CLOCK [patent_app_type] => utility [patent_app_number] => 18/662974 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662974
DERIVING SYSTEM CLOCK FROM GATED DATA CLOCK May 12, 2024 Pending
Array ( [id] => 19588088 [patent_doc_number] => 20240385645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => LATENCY SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 18/659991 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659991
LATENCY SYNCHRONIZATION May 8, 2024 Pending
Array ( [id] => 19405779 [patent_doc_number] => 20240289290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SECURE ENCLAVE SYSTEM-IN-PACKAGE [patent_app_type] => utility [patent_app_number] => 18/655486 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655486
SECURE ENCLAVE SYSTEM-IN-PACKAGE May 5, 2024 Pending
Array ( [id] => 20323180 [patent_doc_number] => 20250335268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => DYNAMIC OPTIMIZATION OF POWER CONSUMPTION IN STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/649113 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649113
DYNAMIC OPTIMIZATION OF POWER CONSUMPTION IN STORAGE SYSTEMS Apr 28, 2024 Pending
Array ( [id] => 19695055 [patent_doc_number] => 20250013600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => LINK LAYER-PHY INTERFACE ADAPTER [patent_app_type] => utility [patent_app_number] => 18/648122 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648122
LINK LAYER-PHY INTERFACE ADAPTER Apr 25, 2024 Pending
Array ( [id] => 20322911 [patent_doc_number] => 20250334999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => CLOCK SYNCHRONIZATION IN A MULTICHIP MODULE [patent_app_type] => utility [patent_app_number] => 18/644595 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644595
CLOCK SYNCHRONIZATION IN A MULTICHIP MODULE Apr 23, 2024 Pending
Array ( [id] => 19385753 [patent_doc_number] => 20240275623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => WIRE FAULT AND ELECTRICAL IMBALANCE DETECTION FOR POWER OVER COMMUNICATIONS CABLING [patent_app_type] => utility [patent_app_number] => 18/642981 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642981
WIRE FAULT AND ELECTRICAL IMBALANCE DETECTION FOR POWER OVER COMMUNICATIONS CABLING Apr 22, 2024 Pending
Array ( [id] => 20296369 [patent_doc_number] => 20250321612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => TIME SYNCHRONIZATION BETWEEN CHASSIS COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/634572 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634572
TIME SYNCHRONIZATION BETWEEN CHASSIS COMPONENTS Apr 11, 2024 Pending
Array ( [id] => 19516387 [patent_doc_number] => 20240348073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => ELECTRONIC APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/625524 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625524
Electronic apparatus, control method, and storage medium Apr 2, 2024 Issued
Array ( [id] => 19513931 [patent_doc_number] => 20240345617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEPARATE CLOCKING FOR COMPONENTS OF A GRAPHICS PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/603883 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603883
SEPARATE CLOCKING FOR COMPONENTS OF A GRAPHICS PROCESSING UNIT Mar 12, 2024 Issued
Array ( [id] => 19711356 [patent_doc_number] => 20250021498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => AREA EFFICIENT ASYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) BUFFER FOR HIGH BANDWIDTH DATA TRANSFER USING EVENT TRANSFER BLOCKS [patent_app_type] => utility [patent_app_number] => 18/601341 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601341
AREA EFFICIENT ASYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) BUFFER FOR HIGH BANDWIDTH DATA TRANSFER USING EVENT TRANSFER BLOCKS Mar 10, 2024 Pending
Array ( [id] => 19971184 [patent_doc_number] => 12339795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Circuit device with multiple parallel data paths [patent_app_type] => utility [patent_app_number] => 18/581522 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581522
Circuit device with multiple parallel data paths Feb 19, 2024 Issued
Array ( [id] => 19391481 [patent_doc_number] => 20240281351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => POWER SAVING BY LOADING REPAIR INFORMATION BEFORE MEMORY DEVICE SENSING [patent_app_type] => utility [patent_app_number] => 18/442704 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442704 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442704
POWER SAVING BY LOADING REPAIR INFORMATION BEFORE MEMORY DEVICE SENSING Feb 14, 2024 Pending
Array ( [id] => 19978802 [patent_doc_number] => 12346277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Systems and methods for hardware acceleration of data masking [patent_app_type] => utility [patent_app_number] => 18/438959 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10100 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438959
Systems and methods for hardware acceleration of data masking Feb 11, 2024 Issued
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