Raymond Ngan Phan

Array ( [id] => 4958042 [patent_doc_number] => 20080272466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'SEMICONDUCTOR SUBSTRATES INCLUDING VIAS OF NONUNIFORM CROSS SECTION AND ASSOCIATED STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/174941 [patent_app_country] => US [patent_app_date] => 2008-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6869 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272466.pdf [firstpage_image] =>[orig_patent_app_number] => 12174941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5340609 [patent_doc_number] => 20090179259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'SEMICONDUCTOR DEVICE WITH (110)-ORIENTED SILICON' [patent_app_type] => utility [patent_app_number] => 12/174030 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6430 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20090179259.pdf [firstpage_image] =>[orig_patent_app_number] => 12174030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500236 [patent_doc_number] => 07919408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Methods for fabricating fine line/space (FLS) routing in high density interconnect (HDI) substrates' [patent_app_type] => utility [patent_app_number] => 12/164977 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3249 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/919/07919408.pdf [firstpage_image] =>[orig_patent_app_number] => 12164977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4634995 [patent_doc_number] => 08013449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Post passivation interconnection schemes on top of the IC chips' [patent_app_type] => utility [patent_app_number] => 12/142825 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 11147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013449.pdf [firstpage_image] =>[orig_patent_app_number] => 12142825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8375220 [patent_doc_number] => 08258011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Method for producing a set of chips mechanically interconnected by means of a flexible connection' [patent_app_type] => utility [patent_app_number] => 12/452137 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2746 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12452137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4756719 [patent_doc_number] => 20080308944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Method for eliminating duo loading effect using a via plug' [patent_app_type] => utility [patent_app_number] => 12/135008 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5234 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0308/20080308944.pdf [firstpage_image] =>[orig_patent_app_number] => 12135008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6239971 [patent_doc_number] => 20100133509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'SEMICONDUCTOR NANOWIRE AND ITS MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/451898 [patent_app_country] => US [patent_app_date] => 2008-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10213 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20100133509.pdf [firstpage_image] =>[orig_patent_app_number] => 12451898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5300322 [patent_doc_number] => 20090294974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'BONDING METHOD FOR THROUGH-SILICON-VIA BASED 3D WAFER STACKING' [patent_app_type] => utility [patent_app_number] => 12/131777 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3849 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20090294974.pdf [firstpage_image] =>[orig_patent_app_number] => 12131777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4695563 [patent_doc_number] => 20080217747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES' [patent_app_type] => utility [patent_app_number] => 12/125508 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5656 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217747.pdf [firstpage_image] =>[orig_patent_app_number] => 12125508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4506548 [patent_doc_number] => 07915057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Manufacturing method of a tray, a socket for inspection, and a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/117341 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8928 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915057.pdf [firstpage_image] =>[orig_patent_app_number] => 12117341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4444544 [patent_doc_number] => 07863105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Image sensor package and forming method of the same' [patent_app_type] => utility [patent_app_number] => 12/117087 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4186 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863105.pdf [firstpage_image] =>[orig_patent_app_number] => 12117087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4955053 [patent_doc_number] => 20080188077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Barrier film deposition over metal for reduction in metal dishing after CMP' [patent_app_type] => utility [patent_app_number] => 12/082188 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2326 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20080188077.pdf [firstpage_image] =>[orig_patent_app_number] => 12082188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4952712 [patent_doc_number] => 20080185736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Multiple selectable function integrated circuit module' [patent_app_type] => utility [patent_app_number] => 12/098465 [patent_app_country] => US [patent_app_date] => 2008-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20080185736.pdf [firstpage_image] =>[orig_patent_app_number] => 12098465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4952598 [patent_doc_number] => 20080185622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'CMOS image sensor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/078552 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2883 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20080185622.pdf [firstpage_image] =>[orig_patent_app_number] => 12078552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5473756 [patent_doc_number] => 20090246922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'METHOD OF FORMING CMOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/056277 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4477 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20090246922.pdf [firstpage_image] =>[orig_patent_app_number] => 12056277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 92079 [patent_doc_number] => 07737033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Etchant and method for fabricating electric device including thin film transistor using the same' [patent_app_type] => utility [patent_app_number] => 12/079008 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 6361 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737033.pdf [firstpage_image] =>[orig_patent_app_number] => 12079008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4515014 [patent_doc_number] => 07932146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Metal gate transistor and polysilicon resistor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/052728 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3173 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932146.pdf [firstpage_image] =>[orig_patent_app_number] => 12052728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5416483 [patent_doc_number] => 20090042370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'METHOD OF CUTTING PCBS' [patent_app_type] => utility [patent_app_number] => 12/051687 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1312 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20090042370.pdf [firstpage_image] =>[orig_patent_app_number] => 12051687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4749732 [patent_doc_number] => 20080157803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'DIE TESTING USING TOP SURFACE TEST PADS' [patent_app_type] => utility [patent_app_number] => 12/047907 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5619 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157803.pdf [firstpage_image] =>[orig_patent_app_number] => 12047907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 221956 [patent_doc_number] => 07609502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Protective device' [patent_app_type] => utility [patent_app_number] => 12/072818 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 11285 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/609/07609502.pdf [firstpage_image] =>[orig_patent_app_number] => 12072818 [rel_patent_id] =>[rel_patent_doc_number] =>)