Search

Raymond Ngan Phan

Examiner (ID: 6794)

Most Active Art Unit
2111
Art Unit(s)
2186, 2305, 2787, 2185, 2781, 2181, 2175, 2111
Total Applications
1838
Issued Applications
1676
Pending Applications
92
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18614403 [patent_doc_number] => 20230281140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => STATUS CHECK USING SIGNALING [patent_app_type] => utility [patent_app_number] => 18/114617 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/114617
Status check using signaling from a memory device Feb 26, 2023 Issued
Array ( [id] => 20130910 [patent_doc_number] => 12373223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => System and method for validation and correction of metadata in containerized software enviornments [patent_app_type] => utility [patent_app_number] => 18/110450 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3451 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110450 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110450
System and method for validation and correction of metadata in containerized software enviornments Feb 15, 2023 Issued
Array ( [id] => 18454040 [patent_doc_number] => 20230195320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SYSTEMS AND METHODS FOR INTEGRATING A COMPUTE RESOURCE WITH A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/108575 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 61367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/108575
SYSTEMS AND METHODS FOR INTEGRATING A COMPUTE RESOURCE WITH A STORAGE DEVICE Feb 9, 2023 Pending
Array ( [id] => 19383086 [patent_doc_number] => 20240272956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => TECHNIQUES FOR SEGMENTATION OF DATA PROCESSING WORKFLOWS IN INSTRUMENT SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/166914 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166914
Techniques for segmentation of data processing workflows between instrument systems and associated computing devices Feb 8, 2023 Issued
Array ( [id] => 19383086 [patent_doc_number] => 20240272956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => TECHNIQUES FOR SEGMENTATION OF DATA PROCESSING WORKFLOWS IN INSTRUMENT SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/166914 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166914
Techniques for segmentation of data processing workflows between instrument systems and associated computing devices Feb 8, 2023 Issued
Array ( [id] => 19522583 [patent_doc_number] => 12124306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Visual or acoustic project support in using an electric appliance with a battery pack [patent_app_type] => utility [patent_app_number] => 18/166157 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5302 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166157
Visual or acoustic project support in using an electric appliance with a battery pack Feb 7, 2023 Issued
Array ( [id] => 19706038 [patent_doc_number] => 12200090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => Multiphase clock generation with automatic skew and amplitude control [patent_app_type] => utility [patent_app_number] => 18/106047 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/106047
Multiphase clock generation with automatic skew and amplitude control Feb 5, 2023 Issued
Array ( [id] => 19267313 [patent_doc_number] => 20240211015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/105258 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105258
Memory structure Feb 2, 2023 Issued
Array ( [id] => 19669164 [patent_doc_number] => 12181910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Timing margin sensor [patent_app_type] => utility [patent_app_number] => 18/104233 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5234 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104233 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104233
Timing margin sensor Jan 30, 2023 Issued
Array ( [id] => 18925100 [patent_doc_number] => 20240028104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => IMPLEMENTATION OF A POWER STAGE IN A MULTI-PHASE VOLTAGE REGULATOR [patent_app_type] => utility [patent_app_number] => 18/161102 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161102 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/161102
Communicating a desired power state to a power stage from a phase controller in a power supply Jan 29, 2023 Issued
Array ( [id] => 19235909 [patent_doc_number] => 20240193104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => COMPUTER SYSTEM WITH FLEXIBLE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/156251 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156251 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156251
Computer system having multiple nodes with flexible configurable architecture Jan 17, 2023 Issued
Array ( [id] => 19283513 [patent_doc_number] => 20240219989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => System For Maintaining A Computer In An Active State [patent_app_type] => utility [patent_app_number] => 18/092293 [patent_app_country] => US [patent_app_date] => 2022-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092293
System For Maintaining A Computer In An Active State Dec 30, 2022 Pending
Array ( [id] => 18349397 [patent_doc_number] => 20230137508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING [patent_app_type] => utility [patent_app_number] => 18/092074 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092074
Area-efficient scalable memory read-data multiplexing and latching Dec 29, 2022 Issued
Array ( [id] => 19267312 [patent_doc_number] => 20240211014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/146733 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146733
POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION Dec 26, 2022 Pending
Array ( [id] => 19267312 [patent_doc_number] => 20240211014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/146733 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146733
POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION Dec 26, 2022 Pending
Array ( [id] => 19267321 [patent_doc_number] => 20240211023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/146811 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146811
Buffer display data in a chiplet architecture Dec 26, 2022 Issued
Array ( [id] => 19167223 [patent_doc_number] => 11983128 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-14 [patent_title] => Multidimensional and multiblock tensorized direct memory access descriptors [patent_app_type] => utility [patent_app_number] => 18/067109 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18505 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067109
Multidimensional and multiblock tensorized direct memory access descriptors Dec 15, 2022 Issued
Array ( [id] => 18280943 [patent_doc_number] => 20230096415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => COLLECTION OF RUNTIME INFORMATION FOR DEBUG AND ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/073056 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073056
Collection of runtime information for debug and analysis, including by aggregating status information into a standardized message format and timestamping Nov 30, 2022 Issued
Array ( [id] => 19189988 [patent_doc_number] => 20240168901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SYSTEMS AND METHODS FOR MANAGING INFORMATION ACROSS MULTIPLE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/989446 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989446
SYSTEMS AND METHODS FOR MANAGING INFORMATION ACROSS MULTIPLE APPLICATIONS Nov 16, 2022 Abandoned
Array ( [id] => 18734764 [patent_doc_number] => 11803495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Method for allocating addresses to a plurality of bus subscribers in a bus system that includes a master module and bus system having a master module and a plurality of bus subscribers [patent_app_type] => utility [patent_app_number] => 17/976941 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5488 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/976941
Method for allocating addresses to a plurality of bus subscribers in a bus system that includes a master module and bus system having a master module and a plurality of bus subscribers Oct 30, 2022 Issued
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